Single instruction stream parallelism is greater than two

Butler, Michael; Yeh, Tse-Yu; Patt, Yale N.; Alsup, Mitch; Scales, Hunter; Shebanow, Michael

doi:10.1145/115952.115980

Cited by 91 publications

(8 citation statements)

References 16 publications

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“…Statistiquement, la probabilité d'occurence des dépendances croît avec le nombre d'instructions que l'on désire exécuter en parallèle. Autrement dit, le parallélisme est restreint dans chaque application et séquence d'instructions (Wall, 1991;Butler et al, 1991). En pratique, des techniques particulières sont utilisées pour limiter l'effet de ces dépendances.…”

Section: Définition Du Parallélisme Et Limitationsunclassified

Les architectures parallèles sur puce. Synthèse des architectures multitâches pour les systèmes embarqués

Ventroux¹,

David²

2010

Techniques et sciences informatiques

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Les systèmes embarqués sont aujourd'hui omniprésents et nécessitent des puissances de calcul toujours plus importantes. Les dispositifs électroniques embarqués envahissent notre vie quotidienne et des milliers d'applications ou de fonctionnalités numériques nous accompagnent en permanence. Les architectures de calcul doivent alors être capables d'atteindre un très haut niveau de performance sous de fortes contraintes d'intégration et de consommation d'énergie. Une solution très efficace pour les systèmes embarqués consiste à multiplier le nombre de ressources de calcul sur une même puce. Ce sont les architectures multiprocesseurs. Elles permettent de traiter de multiples tâches en parallèle sur plusieurs ressources de calcul, voire de favoriser l'exécution concurrente de multiples applications. Cet article synthétise l'état de l'art des solutions existantes. ABSTRACT. Embedded systems are today pervasives and need more and more important computation efficiency. Embedded electronic devices overrun our daily life and million of applications and digital functions are permanently around us. In the future, we will see the utilization boom of these services, which will need very highly performing computing architectures under integration and energy consumption constraints. A solution that can be efficiently exploited in embedded systems consists in multiplying the number of computing resources on the same die. These are multiprocessor architectures. They offer the possibility to execute multiple tasks in parallel onto several computing resources and to eventually favour concurrent execution of multiple applications. This article is a survey on existing solutions.

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Section: Définition Du Parallélisme Et Limitationsunclassified

Les architectures parallèles sur puce. Synthèse des architectures multitâches pour les systèmes embarqués

Ventroux¹,

David²

2010

Techniques et sciences informatiques

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“…This is now a major research topic. b) Shortening the execution latencies of load/store instructions is a crucial point for increasing the throughput of the microarchitecture for at least two reasons; first, load/store instructions amount to about 25 -35 % of all instructions [72]. Second, the memory subsystem is typically slower than the processing pipeline.…”

Section: E Approaches To Further Increase the Throughput Of Superscamentioning

confidence: 99%

Decisive aspects in the evolution of microprocessors

Sima

2004

Proc. IEEE

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The incessant demand for higher performance has provoked a dramatic evolution of the microarchitecture of high performance microprocessors. In this paper we focus on major architectural developments which were introduced for a more effective utilization of instruction level parallelism (ILP) in commercial, performance oriented microprocessors. We show that designers increased the throughput of the microarchitecture at the instruction level basically by the subsequent introduction of temporal, issue and intra-instruction parallelism in such a way that exploiting parallelism along one dimension gave rise to the introduction of parallelism along another dimension. Moreover, the debut of each basic technique used to introduce parallel operation along a certain dimension inevitably called for the introduction of further innovative techniques to avoid processing bottlenecks that arise. Pertinent relationships constitute an underlying logical framework for the fascinating evolution of microarchitectures, which is presented in our paper.

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“…As the issue rate of future microprocessors increases, however, the compiler or the hardware will have to extract more instruction-level parallelism from programs by analyzing a larger instruction window. Unfortunately, it is very difficult to extract enough parallelism with a single thread of control even for a small number of functional units [2,10,20].…”

Section: Introductionmentioning

confidence: 99%

The superthreaded processor architecture

Tsai

Huang

Amlo

et al. 1999

IEEE Trans. Comput.

123

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The common single-threaded execution model limits processors to exploiting only the relatively small amount of instruction-level parallelism available in application programs. The superthreaded processor, on the other hand, is a concurrent multithreaded architecture (CMA) that can exploit the multiple granularities of parallelism available in general-purpose application programs. Unlike other CMAs that rely primarily on hardware for run-time dependence detection and speculation, the superthreaded processor combines compiler-directed thread-level speculation of control and data dependences with run-time data dependence verification hardware. This hybrid of a superscalar processor and a multiprocessor-ona-chip can utilize many of the existing compiler techniques used in traditional parallelizing compilers developed for multiprocessors. Additional unique compiler techniques, such as the conversion of data speculation into control speculation, are also introduced to generate the superthreaded code and to enhance the parallelism between threads. A detailed execution-driven simulator is used to evaluate the performance potential of this new architecture. It is found that a superthreaded processor can achieve good performance on complex application programs through this close coupling of compile-time and run-time information.

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Single instruction stream parallelism is greater than two

Cited by 91 publications

References 16 publications

Les architectures parallèles sur puce. Synthèse des architectures multitâches pour les systèmes embarqués

Les architectures parallèles sur puce. Synthèse des architectures multitâches pour les systèmes embarqués

Decisive aspects in the evolution of microprocessors

The superthreaded processor architecture

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