An important design decision in the implementation ofa superscalar processor is the amount of hardware to allocate to the instruction scheduling mechanism. Dynamic scheduling provides, at the cost of (possibly substantial) additional hardware, the potential to improve upon a static schedule by incorporating run-time information in the scheduling decision. In this study we model several different scheduling techniques and machine configurations. We measure the performance of these models on seven integer and floating point benchmarks taken from the SPEC89 suite. We report the results of these measurements and their implications with respect to the design of high performance superscalar processors.
Recent studies have concluded that little parallelism Q 1991 ACM 0-89791 -394-9/91 /0005/0276$1 .50 276 2 The RDF Model of Execution To exploit whatever parallelism exists in the instruction stream, one needs an execution model devoid of artifacts that limit the utilization of that parallelism. The abstract restricted data flow (RDF) paradigm is such a model. It is characterized by three parameters: window size, issue rate, and instruction class latencies.
A bs t r ac tA n instruction set architecture is a contract between the compiler that provides, in response to the high level language program, directives f o r the interpreter to carry out, and the interpreter (aka microarchilecture) that cam'es out those directives. W e recognize that implementation structures of today tend to drive ISA definitions, and in general that is a mistake. From our perspective, the ultimate microengine is one constrained only by flow dependencies, so an ISA that facilitates data-flow execution will likely be beneficial even in the face of new microarchitectures.
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