Single event upset and multiple cell upset modeling in commercial bulk 65 nm CMOS SRAMs and flip-flops

Uznanski,; Gasiot,; Tavernier,; Autran,

doi:10.1109/radecs.2009.5994579

Cited by 10 publications

(5 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…O termo é a constante de tempo de coleta da junção e é a constante de tempo para o estabelecimento inicial da travessia. Para os dispositivos usados neste trabalho, essas constantes são iguais a 200ps para e 10ps para [26]. O termo Q é a constante de carga que a partícula deposita ao longo de sua travessia e L é a profundidade da trilha de coleta de carga.…”

Section: Atrasounclassified

Análise do Comportamento Elétrico e da Robustez à Radiação de Circuitos XOR em Tecnologia Nanométrica FinFET

Oliveira

Meinhardt

2020

Anais Do XI Computer on the Beach - COTB '20

View full text Add to dashboard Cite

Electronic circuits are becoming more susceptible to errorscaused by radiation due to scaling down technological nodeand high operating frequencies [4, 5, 11].This work presentsa comparative analysis of the sensitivity radiation fordifferent XOR gate topologies 16 nm. The doors wereimplemented considering two different devices:Complementary Metal-Oxide Semiconductor (CMOS bulk)and Fin Field-Effect Transistor (FinFET) and two logics:Complementary Logic (CMOS logic) and Logic PassageTransistor (PTL). To allow a more detailed comparison, thiswork also discusses the critical delay results, power and thePower-Delay Product (PDP), a metric that defines thepower dissipated by the circuit to perform an operation, foreach version of XOR. The doors PTL-based XORs showedsuperior improvements 13% for the critical delay and 11%for the PDP in relation to CMOS logic. The topologies of thePTL family still showed greater robustness against the effectsof radiation when compared to ports implemented withCMOS logic, with a Linear Energy Transfer (LET) beingalmost 30% higher for CMOS devices and approximately20% higher for FinFET devices. In addition, circuits basedon FinFET are about 70% faster, have a PDP 80% smallerand are approximately 300x more robust than CMOStechnology, with an improvement in the LET threshold ofboth logical families evaluated.

show abstract

Section: Atrasounclassified

Análise do Comportamento Elétrico e da Robustez à Radiação de Circuitos XOR em Tecnologia Nanométrica FinFET

Oliveira

Meinhardt

2020

Anais Do XI Computer on the Beach - COTB '20

View full text Add to dashboard Cite

show abstract

“…The charge diffusion and collection mechanisms need to be modeled using analytical [68], [61], [77] or simplified physic equations [69], [80]. The transport mechanisms of the induced charges can be based on ambipolar diffusion model [91] taking into account recombination processes [68], [79] and carrier-carrier scattering phenomenon [61]. The collection mechanisms of induced charges must be based on dynamic collection model [68] which leads to take into account the modulation of the electrical field at the junction between the diffusion regions (drain and source) and the substrate.…”

Section: A Toward Integrated "Framework" For Set Modeling In Electromentioning

confidence: 99%

“…The collection mechanisms of induced charges must be based on dynamic collection model [68] which leads to take into account the modulation of the electrical field at the junction between the diffusion regions (drain and source) and the substrate. These models are layout and technology dependent, as presented in [57], [68], [69], [79], [80]. The inputs of these models can be provided by foundries, designers or from the ITRS roadmaps.…”

Section: A Toward Integrated "Framework" For Set Modeling In Electromentioning

confidence: 99%

Modeling Single Event Transients in Advanced Devices and ICs

Artola

Gaillardin

Hubert

et al. 2015

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

The ability for Single Event Transients (SETs) to induce soft errors in Integrated Circuits (ICs) was predicted for the first time by Wallmark and Marcus in the early 60's [1] and was confirmed to be a serious issue thirty years later. In the 90's microelectronic technologies reached the "deep submicron" era, allowing high density ICs working at frequencies faster than hundreds of MHz. This new paradigm changed the status of SETs to become a major source of reliability losses. Huge efforts have thus been made to characterize SETs in microelectronics, either using experiments or by simulation, in order to reveal key factors leading to SET occurrence, propagation and capture in modern ICs. In this context, modeling and simulation are of primary importance to get accurate SET predictions. This paper focuses on modeling SETs in innovative electronic devices which involves modeling steps at different scales, from ionizing particle to circuit response. After a brief review of the state-of-the art of modeling at each scale, this paper will discuss current capabilities and intrinsic limitations of SET modeling, the incoming challenges in advanced devices and ICs, and finally the methodologies to improve SET simulation and prediction for future technologies.

show abstract

“…To reduce the amount of beam time needed to characterize the radiation tolerance of electronic devices, and to mitigate design errors during development, simulation tools should be utilized prior to characterizing the radiation tolerance in a beam. Simulation tools which can model radiation effects are either already developed or in continuous development [106,107,108]. By calibrating the charge collection models to be compatible with a wide supply voltage range, and by verifying the model correspondence to experimental results, a powerful tool for design of low-power radiation tolerant circuit design may be realized.…”

Section: Recommendations For Further Workmentioning

confidence: 99%

Low-power subthreshold to above threshold level shifters in 90nm and 65nm process

Hasanbegovic

Aunet

2011

Microprocessors and Microsystems

View full text Add to dashboard Cite

Single event upset and multiple cell upset modeling in commercial bulk 65 nm CMOS SRAMs and flip-flops

Cited by 10 publications

References 9 publications

Análise do Comportamento Elétrico e da Robustez à Radiação de Circuitos XOR em Tecnologia Nanométrica FinFET

Análise do Comportamento Elétrico e da Robustez à Radiação de Circuitos XOR em Tecnologia Nanométrica FinFET

Modeling Single Event Transients in Advanced Devices and ICs

Low-power subthreshold to above threshold level shifters in 90nm and 65nm process

Contact Info

Product

Resources

About