Abstract:The ability for Single Event Transients (SETs) to induce soft errors in Integrated Circuits (ICs) was predicted for the first time by Wallmark and Marcus in the early 60's [1] and was confirmed to be a serious issue thirty years later. In the 90's microelectronic technologies reached the "deep submicron" era, allowing high density ICs working at frequencies faster than hundreds of MHz. This new paradigm changed the status of SETs to become a major source of reliability losses. Huge efforts have thus been made … Show more
“…This paper shows the structural CMOS with and without radiation, and variation of electrical properties of device under various radiations doses and proposes a modified CMOS circuit that mitigates radiation effect by improving switch point in I-V characteristic. To redesign the circuit for radiation resistance; the radiation hardened inverter circuit is implemented in each stage of Voltage Controlled Oscillator (VCO) design [4], [5].…”
Rradiation effect causes some major impact on CMOS devices, such as the switch point, change output rail voltage, and the increased leakage current. If radiation is high, proper inverter operation fails. We suggest a scheme to maintain the output voltage by making V gs negative when the NMOS cuts off. This paper shows the structural CMOS with and without radiation and variation of electrical properties of device under various radiations doses and proposes a modified CMOS circuit which mitigates radiation effects by improving switch point in I-V characteristic. In order to redesign the circuit for radiation resistance; the above radiation hardened inverter circuit is implemented in each of Voltage Controlled Oscillator (VCO) gates using Radiation Hardened By Design (RDBD) technique.
“…This paper shows the structural CMOS with and without radiation, and variation of electrical properties of device under various radiations doses and proposes a modified CMOS circuit that mitigates radiation effect by improving switch point in I-V characteristic. To redesign the circuit for radiation resistance; the radiation hardened inverter circuit is implemented in each stage of Voltage Controlled Oscillator (VCO) design [4], [5].…”
Rradiation effect causes some major impact on CMOS devices, such as the switch point, change output rail voltage, and the increased leakage current. If radiation is high, proper inverter operation fails. We suggest a scheme to maintain the output voltage by making V gs negative when the NMOS cuts off. This paper shows the structural CMOS with and without radiation and variation of electrical properties of device under various radiations doses and proposes a modified CMOS circuit which mitigates radiation effects by improving switch point in I-V characteristic. In order to redesign the circuit for radiation resistance; the above radiation hardened inverter circuit is implemented in each of Voltage Controlled Oscillator (VCO) gates using Radiation Hardened By Design (RDBD) technique.
“…In this sense, Monte Carlo simulation tools have solid foundations to be used in the study of radiation effects on electronics [9]. There are many works in the literature which propose the research of radiation effects on electronics exploiting simulations and avoiding the time consuming and expensive radiation campaigns [10][11][12][13][14][15][16][17]. Mixed-mode Technology Computer-Aided Design (TCAD) simulations have been vastly used to understand the main mechanisms in SEEs on electronics.…”
Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event Transient (SET) effects were considered irrelevant compared to the data rupture caused by Single-Event Upset (SEU) effects. However, the importance of considering SET in Very-Large-System-Integration (VLSI) circuits increases given the reduction of the transistor dimensions and the logic data path depth in advanced technology nodes. Accordingly, the threat of SET in electronics systems for space applications must be carefully addressed along with the SEU characterization. In this work, a systematic prediction methodology to assess and improve the SET immunity of digital circuits is presented. Further, the applicability to full-custom and cell-based design methodologies are discussed, and an analysis based on signal probability and pin assignment is proposed to achieve a more application-efficient SET-aware optimization of synthesized circuits. For instance, a SET-aware pin assignment can provide a reduction of 37% and 16% on the SET rate of a NOR gate for a Geostationary Orbit (GEO) and the International Space Station (ISS) orbit, respectively.
“…The phenomena of an unwanted upset of 1 to 0 or 0 to 1 in a memory cell such as an SRAM cell, level sensitive latch or flip-flop (generally sequential logic) caused by an energetic particle strike is called single event upset (SEU) [1][2][3]. Particle strikes could incur an unwanted glitch (a voltage pulse) in the combinational logic that is called single event transient (SET) [4][5][6][7].…”
Section: Introductionmentioning
confidence: 99%
“…To combat with the aforementioned soft errors, various techniques in all levels of abstraction are suggested [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. One costbenefit technique for improving the robustness of digital circuits against soft errors is radiation hardening by design [1,3,[7][8][9][10].…”
Section: Introductionmentioning
confidence: 99%
“…As can be found in the figure, there are two latches including one for storing the logic value that is for being written to IO pad and the other for the logic data value read from the pad. As discussed in [1][2][3][4][5][6], generally latches are prone to be affected by energetic particle strikes dramatically. Furthermore, the SETs came from combinational parts of the circuit.…”
Abstract-This article proposes a radiation hardened parallel IO port capable of tolerating radiation induced soft errors including single event upsets (SEUs) as well as single event transients (SETs). To investigate the soft error tolerance capability of the proposed design, we simulated it using the Cadence tool and showed its offered advantages. Comparing with the conventional and well-known TMR IO port, the proposed architecture results in less hardware redundancy and design cost. Through an analytical analysis, we also showed that, our design has lower failure probability than the TMR approach. It also is notable that, among the considered previous counterparts, our proposed design is the only one that is capable of tolerating both the SEUs and SETs.
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