Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits

IEEE Trans. Aerosp. Electron. Syst.

Fan

Liang

et al. 2022

With the reduction of technology nodes now reaching 2nm, circuits become increasingly susceptible to external perturbations. Thereby, soft errors, such as single-node-upset (SNU), singleevent-transient (SET), double-node-upset (DNU), and even triple-node-upset (TNU), must be considered for safety-critical applications. This paper first presents four advanced circuit components (i.e., advanced voters), that have very small overhead compared with the traditional voters. The proposed Advanced Triple-Modular-Redundancy (ATMR) and Advanced Quadruple-Modular-Redundancy (AQMR) voters only consist of four and six inverters, respectively, to provide effective tolerance against SNUs and DNUs. To further filter SETs, a Schmitt-trigger (ST) instead of an inverter at the output-level is used to construct the ATMR-ST and AQMR-ST voters. These proposed voters can also be extended to tolerate TNUs. Next, these voters are used for latch hardening, so that this paper also presents a series of voter-based latch designs, to ensure high reliability with cost-effectiveness. Simulation results demonstrate the node-upset tolerance and/or SET-filterability of the proposed voters and voter-based latches, respectively. Simulation results also demonstrate that the proposed ATMR voter can reduce delay, power, and area by 55.2%, 32.8%, and 32.2%, respectively, compared with the traditional TMR voter; the proposed so-called HITTSFL latch can reduce delay, power, and area by 78.9%, 15.8%, and 28.6%, respectively, compared with the state-ofthe-art TNU hardened latch (TNUHL).

Section: Introductionmentioning

confidence: 99%

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications

IEEE Trans. Aerosp. Electron. Syst.

Fan

Liang

et al. 2022

“…In a combinational logic circuit, such a particle-striking can cause a transient pulse, i.e., an SET, at the output of the affected logic gate. If there is at least one sensitized-path from the affected gate to a downstream storage element, the SET may propagate to the storage element [3]. If the SET duration is large enough and matches the input-value-sampling window of the storage element, the SET will cause invalid value-retention in the storage element.…”

Section: Introductionmentioning

confidence: 99%

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications

2020 IEEE International Symposium on Circuits and Systems (ISCAS)

Cui

et al. 2020

This paper presents a novel dual-interlocked storagecell (DICE)-based double-node-upset (DNU) self-recoverable, namely DURI-FF, in the nano-scale CMOS technology. The master latch of the DURI-FF cell consists of three transmission gates (TGs) and three interlocked DICEs with three common nodes. The common nodes are connected to TGs for value initialization. The slave latch of the DURI-FF cell comprises six TGs, six inverters and three interlocked DICEs. The outputs of the inverters respectively feed the internal nodes of the slave latch. The interlocked DICEs make the master latch and the slave latch DNU self-recoverable. Simulation results validate the DNU self-recoverability of the proposed DURI-FF cell. Moreover, compared with the state-of-the-art hardened flip-flop cells, the proposed DURI-FF cell achieves roughly 43% delay reduction at the cost of moderate silicon area and power dissipation.

“…In nano-scale CMOS technologies, a high-energy strikingparticle can easily invalidly change the logic state of a node in a storage cell, resulting in an SNU; in a combinational circuit, a high-energy striking-particle can easily result in a transient faulty pulse at the output of a logic gate, i.e., an SET pulse. If an SET propagates through logic gates arriving at a downstream storage cell, it may be captured by the cell, resulting in invalid value-retention [3]. However, in the advanced highly-integrated nano-scale CMOS technologies, due to charge-sharing, a high-energy striking-particle can unfortunately simultaneously change the logic states of double nodes in a storage cell, resulting in a DNU.…”

Section: Introductionmentioning

confidence: 99%

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications

2020 57th ACM/IEEE Design Automation Conference (DAC)

Feng

Zhao

et al. 2020

This paper proposes a cost-effective, high-impedancestate (HIS)-insensitive, triple-node-upset (TNU)-tolerant and single-event-transient (SET)-filterable latch, namely HITTSFL, to ensure high reliability with low-cost. The latch mainly comprises an output-level SET-filterable Schmitt-trigger and three inverters that make the values stored in three parallel single-node-upset (SNU)-recoverable dual-interlocked-storagecells (DICEs) converge at a common node to tolerate any possible TNU. The latch does not use C-elements to be insensitive to the HIS. Simulation results demonstrate the TNU-tolerability and SET-filterability of the proposed HITTSFL latch. Moreover, due to the use of clock-gating technologies and fewer transistors, the proposed latch can reduce delay, power, and area by 76.65%, 6.16%, and 28.55%, respectively, compared with the state-of-theart TNU hardened latch (TNUHL) that cannot filter SETs.