Single-Event Analysis and Hardening of Mixed-Signal Circuit Interfaces in High-Speed Communications Devices

Armstrong, S. E.; Blaine, R. W.; Holman, W.T.; Massengill, L.W.

doi:10.1109/tns.2012.2194166

Cited by 4 publications

(4 citation statements)

References 10 publications

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“…Charge sharing is also exploited to mitigate SET in analog circuits. Common-centroid [9] and differential charge cancellation (DCC) [10][11][12] techniques promote charge sharing for analog SET (ASET) mitigation in differential stages, which can significantly mitigate ASET perturbation but lead to complex wiring overhead and larger load capacitance. Also, those techniques can only be applied in differential designs.…”

Section: Introductionmentioning

confidence: 99%

Pulse quenching based radiation-hardened by design technique for analog single-event transient mitigation on an operational amplifier in 28 nm bulk CMOS process

Liu

Sun

et al. 2020

Semicond. Sci. Technol.

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In nanometer bulk CMOS processes, multi-node charge collection induced by a heavy-ion strike is prevalent. Pulse quenching caused by charge sharing between the struck node (termed as active device) and the following gate (termed as passive device) has been widely studied in digital circuits. This paper firstly demonstrates that the pulse quenching effect also exists between the adjacent stages of analog circuits and can be used to mitigate analog single-event transient (ASET) perturbation. Contrary to digital circuits, whose propagated SET is minimized with the charge collected by passive device maximized, simulation results indicate that there is an optimal spacing between the active and passive devices in analog circuits. When the spacing is too close, the SET induced by the hit node is efficiently mitigated by pulse quenching effect, but the disturbance caused by the charge sharing collection in passive device becomes dominant. Simulation results show that pulse quenching effect has a dual role in ASET mitigation. This paper provides innovative guidance to the radiation-hardening design for analog circuits.

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Section: Introductionmentioning

confidence: 99%

Pulse quenching based radiation-hardened by design technique for analog single-event transient mitigation on an operational amplifier in 28 nm bulk CMOS process

Liu

Sun

et al. 2020

Semicond. Sci. Technol.

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“…Analog single-event transients (ASETs) are the transient fluctuations occurring when high energy particles are injected into sensitive circuit nodes in analog circuits, and which belong to the broader category of single event effects (SEEs). ASETs can damage the reliable function of a circuit, resulting in transient or permanent failure [1][2][3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Current mirror featuring DTMOS for analog single‐event transient mitigation in space application

Liu

Sun

et al. 2020

Semicond. Sci. Technol.

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Dynamic threshold-voltage MOSFETs (DTMOSs) with bulk and gate tied together are commonly used in ultra-low voltage applications. Since the threshold voltage of the device is a function of its gate voltage, and the current-driving capability is boosted as the gate-source voltage increases, it has the potential to be applied in the community of radiation-hardened IC circuits. This paper firstly demonstrates that DTMOS is particularly suitable for analog single-event transient (ASET) mitigation in cascode current mirrors with negligible penalty. A basic current mirror and a cascode current mirror are modelled to analyze the devices in DTMOS configuration, and compare radiation performance with standard MOSFETs. Simulation results demonstrate that the DTMOS scheme reduces charge collection, and suppresses single-event effect-induced perturbation effectively in the cascode current mirror, while playing a detrimental role in basic current mirrors due to the well-known bipolar effect. This technique provides a novel method for mitigating ASET disturbances for the designers of spaceborne ICs.

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“…Integrated Circuits (ICs) for space-and-satellite applications are subject to various radiation effects such as Total Ionizing Dose (TID) [1] and Single-Event-Effects (SEEs) [2]. To mitigate said radiation effects, the Radiation-Hardening-By-Design (RHBD) approach [3][4][5][6] is increasingly prevalent by leveraging on the commercially-available advanced CMOS processes.…”

Section: Introductionmentioning

confidence: 99%

“…It is generally agreed in the space community that SEE is more pronounced than TID in advanced deep submicron CMOS processes (typically the technology node ≤130nm). Hence, the SEE mechanisms therein and the pertinent RHBD techniques have been widely reported [5,6]. Nonetheless, in view of the accumulative effect of TID (as opposed to the intermittent effect of SEEs), it is still highly desirable to achieve minimal TID to extent the lifespan of satellite.…”

Section: Introductionmentioning

confidence: 99%

Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process

Jiang

Shu

Chong

et al. 2016

2016 IEEE International Symposium on Circuits and Systems (ISCAS)

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Single-Event Analysis and Hardening of Mixed-Signal Circuit Interfaces in High-Speed Communications Devices

Cited by 4 publications

References 10 publications

Pulse quenching based radiation-hardened by design technique for analog single-event transient mitigation on an operational amplifier in 28 nm bulk CMOS process

Pulse quenching based radiation-hardened by design technique for analog single-event transient mitigation on an operational amplifier in 28 nm bulk CMOS process

Current mirror featuring DTMOS for analog single‐event transient mitigation in space application

Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process

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