Single-Cycle Bit Permutations with MOMR Execution

Lee, Ruby B.; Yang, Xiao; Shi, Zhijie

doi:10.1007/s11390-005-0577-0

Cited by 4 publications

(9 citation statements)

References 16 publications

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“…Each level is controlled by four key bits for a total 24 bits per key. Efficient implementations produce arbitrary permutations in one cycle of a high-performance microprocessor when pipelined [8]. Linear transformations over the field F2 can be implemented using only NOT and XOR gates.…”

Section: Classes Of Reversible Transformationsmentioning

confidence: 99%

“…Therefore, they are the main source of overhead in the proposed bus-locking scheme. This is why we use permutation circuits from [8] that have already been optimized and implemented within microprocessor designs. Such circuits require only 2n log 2 n MUX gates which is considerably smaller than an n-bit multiplier, for example.…”

Section: Minimizing Design Overheadmentioning

confidence: 99%

“…Such circuits require only 2n log 2 n MUX gates which is considerably smaller than an n-bit multiplier, for example. Their logic depth, when pipelined, is log 2 n, which is comparable to an ALU for modern designs, producing permutation every cycle [8]. Thus timing is not degraded and only one cycle of latency is added for bus communications.…”

Section: Minimizing Design Overheadmentioning

confidence: 99%

“…The countermeasure for attack (i), brute-force key testing, is to increase key length so as to make the attack infeasible for modern circuits. Thus we perform a comprehensive analysis of Benes networks used in [8] to show that this method is secure.…”

Section: Key Strength Evaluationmentioning

confidence: 99%

“…The circuits described in [8] for arbitrary bit permutations consist of 2 log 2 n stages of n MUX gates each. n/2 bits control each stage for a total of n log 2 n key bits.…”

Section: Key Strength Evaluationmentioning

confidence: 99%

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Protecting bus-based hardware IP by secret sharing

Roy

Koushanfar

Markov

2008

Proceedings of the 45th Annual Design Automation Conference

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Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation is applicable to a broad category of electronic systems with a primary bus. Such designs include (1) numerous IP offerings for USB, PCI, PCI-E, AMBA and other bus standards typically used in system-on-a-chip designs and computer peripherals, (2) SRAM-based FPGAs that are programmed through an input bus, (3) general-purpose and embedded microprocessors, including soft cores, (4) DSPs, (5) network processors, and (6) game consoles. Our key insight is that such designs can be locked by scrambling the central bus by controlled reversible bit-permutations and substitutions. To securely establish a unique code per chip to control bus scrambling, we employ true random number generators and Diffie-Hellman cryptography during activation.

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Section: Classes Of Reversible Transformationsmentioning

confidence: 99%

Section: Minimizing Design Overheadmentioning

confidence: 99%

Section: Minimizing Design Overheadmentioning

confidence: 99%

Section: Key Strength Evaluationmentioning

confidence: 99%

“…The circuits described in [8] for arbitrary bit permutations consist of 2 log 2 n stages of n MUX gates each. n/2 bits control each stage for a total of n log 2 n key bits.…”

Section: Key Strength Evaluationmentioning

confidence: 99%

See 3 more Smart Citations

Protecting bus-based hardware IP by secret sharing

Roy

Koushanfar

Markov

2008

Proceedings of the 45th Annual Design Automation Conference

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Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors

Hilewitz

Lee

2008

J Sign Process Syst Sign Image Video Technol

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Advanced bit manipulation operations are not efficiently supported by commodity word-oriented microprocessors. Programming tricks are typically devised to shorten the long sequence of instructions needed to emulate these complicated bit operations. As these bit manipulation operations are relevant to applications that are becoming increasingly important, we propose direct support for them in microprocessors. In particular, we propose fast bit gather (or parallel extract), bit scatter (or parallel deposit) and bit permutation instructions (including group, butterfly and inverse butterfly). We show that all these instructions can be implemented efficiently using both the fast butterfly and inverse butterfly network datapaths. Specifically, we show that parallel deposit can be mapped onto a butterfly circuit and parallel extract can be mapped onto an inverse butterfly circuit. We define static, dynamic and loop invariant versions of the instructions, with static versions utilizing a much simpler functional unit. We show how a hardware decoder can be implemented for the dynamic and loopinvariant versions to generate, dynamically, the control signals for the butterfly and inverse butterfly datapaths. The simplest functional unit we propose is smaller and faster than an ALU. We also show that these instructions yield significant speedups over a basic RISC architecture for a variety of different application kernels taken from applications domains including bioinformatics, steganography, coding, compression and random number generation.

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A New Basis for Shifters in General-Purpose Processors for Existing and Advanced Bit Manipulations

Hilewitz

Lee

2009

IEEE Trans. Comput.

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Single-Cycle Bit Permutations with MOMR Execution

Cited by 4 publications

References 16 publications

Protecting bus-based hardware IP by secret sharing

Protecting bus-based hardware IP by secret sharing

Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors

A New Basis for Shifters in General-Purpose Processors for Existing and Advanced Bit Manipulations

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