Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors

Abstract

Advanced bit manipulation operations are not efficiently supported by commodity word-oriented microprocessors. Programming tricks are typically devised to shorten the long sequence of instructions needed to emulate these complicated bit operations. As these bit manipulation operations are relevant to applications that are becoming increasingly important, we propose direct support for them in microprocessors. In particular, we propose fast bit gather (or parallel extract), bit scatter (or parallel deposit) and bit permutation instructions (including group, butterfly and inverse butterfly). We show that all these instructions can be implemented efficiently using both the fast butterfly and inverse butterfly network datapaths. Specifically, we show that parallel deposit can be mapped onto a butterfly circuit and parallel extract can be mapped onto an inverse butterfly circuit. We define static, dynamic and loop invariant versions of the instructions, with static versions utilizing a much simpler functional unit. We show how a hardware decoder can be implemented for the dynamic and loopinvariant versions to generate, dynamically, the control signals for the butterfly and inverse butterfly datapaths. The simplest functional unit we propose is smaller and faster than an ALU. We also show that these instructions yield significant speedups over a basic RISC architecture for a variety of different application kernels taken from applications domains including bioinformatics, steganography, coding, compression and random number generation.

Design of a processor optimized for syntax parsing in video decoders

“…The hardware implementation of an ASIP consists of a general processor with the addition of specific instructions within the ALU, or functional units within the core [4,5]. In short, the software implementation consists in updating the cross compilation tools, usually GCC/GDB.…”

“…but not bit-size operations which are required to extract an element arbitrary. Ongoing research presents various methods [4,7] to implement these bit manipulation operations. The hardware implementation is usually realized using functional units (i.e.…”

“…Researchers have presented methods to efficiently manage bit manipulation operations with results obtained on general purpose processor architectures [8], DSPs [1,5] or applications without real-time constraints [4]. This leads to a lack of exploration of real-time applications implemented on codesign architectures even though they are more and more used.…”

“…It has the following behavior: Although, the ShowNbits function is quite simple, it requires several cycles to build the M bits size word, to shift and to mask (if necessary) the bits. Hence, a specific instruction which processes these operations allows the performance to be improved [4,7].…”

Butterfly and Inverse Butterfly nets integration on Altera NIOS-II embedded processor

“…A very interesting solution is presented in [1], [2], [3] and [4], where the authors present a BMU able to speed up the bit level operations frequently used in the implementation of different algorithms.…”