A New Basis for Shifters in General-Purpose Processors for Existing and Advanced Bit Manipulations

Hilewitz, Yedidya; Lee, R.B.

doi:10.1109/tc.2008.219

Cited by 20 publications

(12 citation statements)

References 13 publications

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“…This incremental cost ∆c(l) for K b plus all existing components of the already implemented 1-subvectors at level l should not exceed the total number of components required in the l-th level of an s-bit full-range logarithmic shifter expressed in (1). Let c exist (l) be the total number of existing components at level l before K b is implemented.…”

Section: B1 Reduction By Logic Reusementioning

confidence: 99%

“…HIFTING is a commonly required and often important operation for data manipulation in many general-purpose micro-processors [1] and embedded digital signal processors, such as low-density parity-check (LDPC) decoder [2], programmable finite impulse response (FIR) filters [3], [4], residue number system (RNS) [5] and reconfigurable multipliers (RM) such as those in discrete cosine transform (DCT) architecture [6]. Fast but expensive s-bit logarithm shifters are usually used in existing designs [1] - [3], [5], [6] to flexibly shift a variable by 0 to s -1 bits at run time. According to [3], more than 40% of the total hardware cost and power consumption of an 8-bit 100-tap programmable FIR filter are due to the logarithmic shifters.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

New Hardware and Power Efficient Sporadic Logarithmic Shifters for DSP Applications

Chen

Chang

Wang

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Shifting an input data by variable amounts is commonly found in arithmetic operations, data encoding and bit-indexing. Although some shift amounts along the entire shift range are not required, the typical realization by a full-range logarithm shifter requires full implementation and therefore suffers from complexity and power overhead. In this paper, the notion of sporadic logarithmic shifter is introduced for the first time, and a new design methodology is proposed for its optimization. By reusing parts of existing substructure of conventional logarithmic shifter or post-multiplexing the hardwired shifts, contagious subranges of desirable shift amounts are successively realized. Synthesis results on 8-bit and 16-bit sporadic logarithmic shifters show average ASIC area and power savings of up to 73.24% and 63.90% respectively, over conventional logarithmic shifters. In addition, by applying the proposed sporadic logarithmic shifters to the DCT architecture, at least 47.5% area savings and 2.9% power savings can be achieved over two constant multipliers based DCT architectures reported in the literature.

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Section: B1 Reduction By Logic Reusementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

New Hardware and Power Efficient Sporadic Logarithmic Shifters for DSP Applications

Chen

Chang

Wang

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…but not bit-size operations which are required to extract an element arbitrary. Ongoing research presents various methods [4,7] to implement these bit manipulation operations. The hardware implementation is usually realized using functional units (i.e.…”

Section: Application-specific Instruction-set Processorsmentioning

confidence: 99%

“…It has the following behavior: Although, the ShowNbits function is quite simple, it requires several cycles to build the M bits size word, to shift and to mask (if necessary) the bits. Hence, a specific instruction which processes these operations allows the performance to be improved [4,7].…”

Section: Software Implementation Of the Syntax Parsingmentioning

confidence: 99%

Design of a processor optimized for syntax parsing in video decoders

Siret

Nezan

Rhatay³

2011

Proceedings of the 2011 Conference on Design &Amp; Architectures for Signal &Amp; Image Processing (DASIP)

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Heterogeneous platforms aim to offer both performance and flexibility by providing designers processors and programmable logical units on a single platform. Processors implemented on these platforms are usually soft-cores (e.g. Altera NIOS) or ASIC (e.g. ARM Cortex-A8). However, these processors still face limitations in terms of performance compared to full hardware designs in particular for real-time video decoding applications. We present in this paper an innovative approach to improve performance using both a processor optimized for the syntax parsing (an Application-Specific Instruction-set Processor) and a FPGA. The case study has been synthesized on a Xilinx FPGA at a frequency of 100 MHz and we estimate the performance that could be obtained with an ASIC.

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“…The benes network [7], which is formed by concatenating a butterfly network and an inverse butterfly network. An n-bit butterfly network consists of lg(n) stages.…”

Section: The Butterfly Network Shiftermentioning

confidence: 99%

An Area Optimized Implementation of Cryptographic Algorithm RC5

Liang

Wang

et al. 2009

2009 5th International Conference on Wireless Communications, Networking and Mobile Computing

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As a widely used symmetrical block cryptographic algorithm, RC5 has the characteristic of variable block length, variable round number and variable key length to satisfy the security need of different application environment. This paper presents an area efficient and reconfigurable hardware circuit. Using loop unrolling technology, the hardware circuit costs less resources by 74.7% compared to the conventional area optimized implementation of RC5 algorithm.

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A New Basis for Shifters in General-Purpose Processors for Existing and Advanced Bit Manipulations

Cited by 20 publications

References 13 publications

New Hardware and Power Efficient Sporadic Logarithmic Shifters for DSP Applications

New Hardware and Power Efficient Sporadic Logarithmic Shifters for DSP Applications

Design of a processor optimized for syntax parsing in video decoders

An Area Optimized Implementation of Cryptographic Algorithm RC5

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