Single-chip FEC codec using a concatenated BCH code for 10 Gb/s long-haul optical transmission systems

Kang

Park

et al. 2010

J Sign Process Syst

This paper presents a two-iteration concatenated Bose-Chaudhuri-Hocquenghem (BCH) code and its highspeed low-complexity two-parallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. A low-complexity syndrome computation architecture and a high-speed dual-processing pipelined simplified inversonless Berlekamp-Massey (DualpSiBM) key equation solver architecture were applied to the proposed concatenated BCH decoder with an aim of implementing a high-speed low-complexity decoder architecture. Two-parallel processing allows the decoder to achieve a high data processing rate required for 100 Gb/s optical communication systems. Also, the proposed two-iteration concatenated BCH code structure with block interleaving methods allows the decoder to achieve 8.91dB of net coding gain performance at 10 −15 decoder output bit error rate to compensate for serious transmission quality degradation. Thus, it has potential applications in next generation forward error correction schemes for 100 Gb/s optical communications.

Section: Conventional Three-iteration Concatenated Bch Codementioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100 Gb/s Optical Communications

Kang

Park

et al. 2010

J Sign Process Syst

“…This technique can improve the error correction capability without increasing the coding rate. The 10 Gb/s concatenated BCH decoder using this code was proposed in [3]. Also, this architecture can be used up to 40 Gb/s systems in its present form simply increasing the clock frequency using the pipelining technique.…”

Section: Conventional Three-iteration Concatenated Bch Codementioning

confidence: 99%

100GB/S two-iteration concatenated BCH decoder architecture for optical communications

2010 IEEE Workshop on Signal Processing Systems

Kang

Park

et al. 2010

This paper presents a two-iteration concatenated BoseChaudhuri-Hocquenghem (BCH) code and its high-speed low-complexity two-parallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. A low-complexity syndrome computation architecture and a high-speed dual-processing pipelined simplified inversonless Berlekamp-Massey (DualpSiBM) key equation solver architecture were applied to the proposed concatenated BCH decoder with an aim of implementing a high-speed low-complexity decoder architecture. The proposed two-iteration concatenated BCH code structure with block interleaving methods allows the decoder to achieve 8.91dB of net coding gain performance at 10 -15 decoder output bit error rate to compensate for serious transmission quality degradation. Thus, it has potential applications in next generation forward error correction schemes for 100 Gb/s optical communications.

“…But, no specific FEC has been determined yet for metro and long-haul systems. Also, the concatenated BCH FEC decoder architecture proposed in [4] is difficult to achieve 100 Gb/s throughput in its present form.…”

Section: Introductionmentioning

confidence: 99%

High-Speed Two-Parallel Concatenated BCH-Based Super-FEC Architecture for Optical Communications

Yoon

IEICE Trans. Fundamentals

2010

This paper presents a high-speed Forward Error Correction (FEC) architecture based on concatenated Bose-Chaudhuri-Hocquenghem (BCH) for 100-Gb/s optical communication systems. The concatenated BCH code consists of BCH(3860, 3824) and BCH(2040, 1930), which provides 7.98 dB net coding gain at 10 −12 corrected bit error rate. The proposed BCH decoder features a low-complexity key equation solver using an error-locator computation RiBM (ECRiBM) algorithm and its architecture. The proposed concatenated BCH-based Super-FEC architecture has been implemented in 90-nm CMOS standard cell technology with a supply voltage of 1.1 V. The implementation results show that the proposed architecture can operate at a clock frequency of 400 MHz and has a throughput of 102.4-Gb/s for 90-nm CMOS technology.