Simultaneous Two-Dimensional Cell Layout Compaction Using MILP with ASTRAN

Abstract

This paper describes a technique to compact cell layouts efficiently using Mixed-Integer Linear Programming. By using binary variables we were able not only to model the conditional design rules, which apply to technology nodes down to 65nm, but also to compact layouts in the two-dimensions simultaneously. This technique was applied to a transistor network layout synthesis tool called ASTRAN which is being used to generate on-demand cells with unrestricted transistor network structure. We demonstrate in this paper that our technique is able to generate dense cell layouts, competitive with manually designed cells.

Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)

“…Then, if there is any FET be placed in i th cell row or the cell row larger than i, the W i is set to W max . Otherwise, the W i is 0 as described in (8). With (8), we can minimize the cell area with the considerations of single-row and multi-row structures simultaneously.…”

“…In this section, we compare the SDC areas of adaptive cell row number, triple-row (TR), double-row (DR), and single-row (SR) [17] in 2.5T CFET cell structure. For demonstrating the cell area benefit of adaptive cell row SDC structure while synthesizing each SDC, we use objective (9) and equation (8) to generate the minimum cell area with optimum cell row (Opt. CR) in our framework.…”

“…SDC Synthesis Automation. For single-row SDC synthesis, several works have reported full automation of cell layout covering transistor-level placement and in-cell routing together [7], [8], but these approaches are not applicable in the multi-patterning technologies in sub-5nm. Also, several SDC synthesis automation works have been proposed for multipatterning technology [9], [10], [11], but the placement and routing are performed in separate operations.…”

A routability-driven complimentary-FET (CFET) standard cell synthesis framework using SMT

“…SDC Synthesis Automation. In [9,25], authors reported full automation of cell layout covering transistor-level placement and in-cell routing together, but these approaches are not applicable in the multi-patterning technologies in sub-5nm. For multi-patterning technology nodes, [7,10,12] proposed SDC synthesis automation, but the placement and routing are performed in separate operations.…”