Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)

Abstract

With the relentless scaling of technology nodes, the track number reduction of conventional (Conv.) cell is starting to reach its limitations due to limited routing resources, lateral P-N separations, and performance requirements. As a result, to exploit the benefits of 3D architectures, Complementary-FET (CFET) technology, which stacks P-FET on N-FET or vice versa, is proposed to release the restriction of P-N separation and reduce in-cell routing congestion by enabling P-N direct connections. However, CFET standard cell (SDC) synthesis demands a holistic reconsideration of multi-row structure to maximize the cell and block-level area benefits due to limited in-cell routing tracks and routability that comes from the stacked structure and reduced cell height.In this paper, we propose an SMT (Satisfiability Modulo theories)-based Multi-Row CFET SDC synthesis framework that simultaneously solves place-and-route to minimize the cell area by considering single-row and multi-row placement together. We enable explorations on Upper/Lower M0A/PC routing to leverage the shared-and-split structure across cell rows with the proposed multi-row dynamic complementary pin allocation scheme. We demonstrate that multi-row 2.5T CFET without and with Upper/Lower M0A/PC routing achieve 16.44% and 20.61% on the average reduced cell areas, respectively, compared to 3.5T CFET. Moreover, multi-row 2.5T CFET SDCs achieve 13.43% and 14.40% less block-level area and total wirelength on average compared to 3.5T CFET SDCs.