Simultaneous scheduling, binding and layer assignment for synthesis of vertically integrated 3D systems

Mukherjee, M.; Vemuri, Ranga

doi:10.1109/iccd.2004.1347926

Cited by 14 publications

(4 citation statements)

References 24 publications

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“…Very little has been reported on high-level synthesis systems aimed at 3-D layouts. To the best of our knowledge, only Mukherjee and Vemuri [11,12] have addressed high-level synthesis for 3D ICs. However, their approach seperates the the high-level synthesis tasks from the floorplanning step.…”

Section: Related Workmentioning

confidence: 98%

A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits

Krishnan

Katkoori

2007

8th International Symposium on Quality Electronic Design (ISQED'07)

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Recent progress in the fabrication of three-dimensional integrated circuits has opened up the possibility of exploiting this technology to alleviate performance and power related issues raised by interconnects in nanometer CMOS. Physical synthesis for three-dimensional integrated is substantially different from traditional planar integrated circuits due to the presence of additional constraints of placing circuit blocks in multiple die. To realize the full potential offered by three-dimensional integrated circuits, high-level synthesis of these circuits must take layout-related issues unique to 3-D technology into account during the synthesis process. We present a 3-D layout aware binding algorithm for high-level synthesis that tightly integrates the synthesis tasks of resource binding, assignment of modules to multiple die, 3-D floorplanning, and inter-die via minimization. Since floorplanning and resource binding are interdependent, the algorithm can significantly outperform traditional high-level synthesis flows that seperate these tasks. Compared to a traditional 3-D layout-unaware binding, experiments show that our approach can improve the total wirelength by 29% on average, while the longest netlength is reduced by 21%. In addition, the number of through-die via count is reduced by 27%. These optimizations are achieved with no penalty in chip area.

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Section: Related Workmentioning

confidence: 98%

A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits

Krishnan

Katkoori

2007

8th International Symposium on Quality Electronic Design (ISQED'07)

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“…Some of the constraints including (1),(2),(3),(4),(5),(6) are the same with that of [3][6], and others were designed by us for the purpose of simultaneous resource duplication, resource binding and layer assignment.…”

Section: B Ilp Formulations For Tsv Number Minimizationmentioning

confidence: 99%

“…Under the constraint of floorplaning criteria, Mukherjee and Vemuri [3][4] Proposed an integer linear programming formulation for simultaneous scheduling, binding, and layer assignment, and their objective function was composed of both the number of TSVs and the critical path length. Krishnan and Katkoori [5] proposed a framework to integrate the resource binding and floorplaning problems together in the 3D ICs structure.…”

Section: Introductionmentioning

confidence: 99%

A resource binding technique for TSV number minimization in high-level synthesis of 3D ICs

Cheng

Yen

2011

2011 International Symposium on Integrated Circuits

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Three dimensional integrated circuits allow multiple devices to be stacked on multiple layers. Therefore, utilize the area of each layer efficiently and minimize the number of through silicon vias (TSVs) are crucial to the 3D IC design. In this paper, we propose an integer linear programming (ILP) model to perform simultaneous resource binding and layer assignment in high-level synthesis of 3D ICs. Our objective is to minimize the number of TSVs under both the layer number constraint and the footprint area constraint. By means of duplicating hardware resources properly during resource binding and layer assignment, our approach has obvious improvement in reducing the number of TSVs while not increasing the footprint area. Experimental results show that our methodology is effective indeed for this 3D ICs synthesis problem.

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“…Previous work on high-level synthesis for 3-D integrated circuits include [16], [17], [18], and [19]. The authors of [16] and [17] formulate the high-level synthesis task and the assignment of RTL modules to various 3-D layers, as a Linear Programming problem that generates constraints to run a 3-D constraint-driven floorplanner. However, their approach, separates the the high-level synthesis tasks from the floorplanning step.…”

Section: Introductionmentioning

confidence: 99%

A Timing-driven Binding Algorithm for High-Level Synthesis of Three-dimensional Integrated Circuits

Krishnan¹

2018

IJCA

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As semiconductor technology scaling approaches its limits, 3-D integrated circuits (3-D ICs) have been proposed as one solution to continue the push towards increasing transistor counts in VLSI circuits. Recent progress in the fabrication of three-dimensional (3-D) integrated circuits has opened the possibility of exploiting this technology to alleviate performance and power related issues raised by interconnects in advanced nanometer CMOS VLSI circuits. Physical synthesis for 3-D integrated circuits is substantially different from traditional planar integrated circuits due to the presence of additional constraints of placing circuit modules in multiple silicon layers. To realize the full potential offered by 3-D integrated circuits, high-level synthesis of these circuits must take layout-related issues unique to 3-D technology into account during the synthesis process. This paper presents a 3-D layout-aware timing-driven binding algorithm for designspace exploration during high-level synthesis. The algorithm tightly integrates the synthesis tasks of resource binding, assignment of modules to multiple silicon die, 3-D floorplanning, and through-silicon via (TSV) minimization. Elmore delay models incorporating distributed wire-delays, together with delays introduced by pins and TSVs in a 3-D integrated circuit are used to compute data-transfer delays in a data path. Accurate estimates of individual net delays, obtained from net topologies in 3-D floorplans, are used to compute wire delays. Our experimental results show that a timing-driven binding algorithm for high-level synthesis can improve delays by an average of 12.2% and a maximum of up to 20.65%.

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Simultaneous scheduling, binding and layer assignment for synthesis of vertically integrated 3D systems

Cited by 14 publications

References 24 publications

A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits

A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits

A resource binding technique for TSV number minimization in high-level synthesis of 3D ICs

A Timing-driven Binding Algorithm for High-Level Synthesis of Three-dimensional Integrated Circuits

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