A resource binding technique for TSV number minimization in high-level synthesis of 3D ICs

Abstract

Three dimensional integrated circuits allow multiple devices to be stacked on multiple layers. Therefore, utilize the area of each layer efficiently and minimize the number of through silicon vias (TSVs) are crucial to the 3D IC design. In this paper, we propose an integer linear programming (ILP) model to perform simultaneous resource binding and layer assignment in high-level synthesis of 3D ICs. Our objective is to minimize the number of TSVs under both the layer number constraint and the footprint area constraint. By means of duplicating hardware resources properly during resource binding and layer assignment, our approach has obvious improvement in reducing the number of TSVs while not increasing the footprint area. Experimental results show that our methodology is effective indeed for this 3D ICs synthesis problem.