Simultaneous Memory and Bus partitioning for SoC architectures.

Srinivasan, Suresh; Angiolini, Federico; Ruggiero, Martino; Benini, Luca; Vijaykrishnan, N.

doi:10.1109/socc.2005.1554478

Cited by 7 publications

(4 citation statements)

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“…Mai et al [1] enable manual algorithm execution by largely simplifying the low power optimization problem. The authors of [5,8] target the combined optimization problem of memory and bus partitioning for multi-master, multi-memory systems. Zhuge et al [9] distribute variables between different memory instances to increase digital signal processor (DSP) performance.…”

Section: Related Workmentioning

confidence: 99%

Low power memory allocation and mapping for area-constrained systems-on-chips

2016

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Large fractions of today's embedded systems' power consumption can be attributed to the memory subsystem. In order to reduce this fraction, we propose a mathematical model to optimize on-chip memory configurations for minimal power. We exploit the power reduction effect of splitting memory into subunits with frequently accessed addresses mapped to small memories. The definition of an integer linear programming model enables us to solve the twofold problem of allocating an optimal set of memory instances with varying size on the one hand and finding an optimal mapping of application segments to allocated memories on the other hand. Experimental results yield power reductions of up to 82 % for instruction memory and 73 % for data memory. Area usage, at the same time, deteriorates by only 2.1 %, respectively, 1.2 % on average and even improves in some cases. Flexibility and performance of our model make it a valuable tool for low power system-on-chip design, either for efficient design space exploration or as part of a HW/SW codesign synthesis flow.

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Section: Related Workmentioning

confidence: 99%

Low power memory allocation and mapping for area-constrained systems-on-chips

2016

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“…His work combined memory partitioning and processor partitioning and revealed that both are very important to obtain best system performance. In [11], Srinivasan presented a genetic algorithm based search mechanism to determine a system's configuration on memory and bus that is energyefficiency. Both Xue and Srinivasan addressed memory partitioning in combination with other factors, e.g.…”

Section: Related Workmentioning

confidence: 99%

Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips

Chen

Jantsch

et al. 2010

2010 3rd International Symposium on Parallel Architectures, Algorithms and Programming

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Abstract-On multi-core Network-on-Chips (NoCs), memories are preferably distributed and supporting Distributed Shared Memory (DSM) is essential for the sake of reusing huge amount of legacy code and easy programming. However, the DSM organization imports the inherent overhead of translating virtual memory addresses into physical memory addresses, resulting in negative performance. We observe that, in parallel applications, different data have different properties (private or shared). For the private data accesses, it's unnecessary to perform Virtual-to-Physical address translations. Even for the same datum, its property may be changeable in different phases of the program execution. Therefore, this paper focuses on decreasing the overhead of Virtual-to-Physical address translation and hence improving the system performance by introducing hybrid DSM organization and supporting run-time partitioning according to the data property. The hybrid DSM organization aims at supporting fast and physical memory accesses for private data and maintaining a global and single virtual memory space for shared data. Based on the data property of parallel applications, the run-time partitioning supports changing the hybrid DSM organization during the program execution. It ensures fast physical memory addressing on private data and conventional virtual memory addressing on shared data, improving the performance of the entire system by reducing virtual-to-physical address translation overhead as much as possible. We formulate the run-time partitioning of hybrid DSM organization in order to analyze its performance. A real DSM based multi-core NoC platform is also constructed. The experimental results of real applications show that the hybrid DSM organization with run-time partitioning demonstrates performance advantage over the conventional DSM counterpart. The percentage of performance improvement depends on problem size, way of data partitioning and computation/communication ratio of parallel applications, network size of the system, etc. In our experiments, the maximal improvement is 34.42%, the minimal improvement 3.68%.

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“…Kim et al [33] deal with bus topology and static prioritybased arbitration exploration to determine the best memory port-to-bus mapping for presynthesized memory blocks. More recently, Srinivasan et al [47] present an approach to simultaneously consider bus-topology splitting and memory bank partitioning during synthesis. While they consider a limited design space compared to our approach (they do not consider the effect of communication parameters or different memory types), their focus is on the problem of system energy reduction, which is not currently addressed by our approach.…”

Section: Related Workmentioning

confidence: 99%

“…Data arrays and groups of scalars in the application are grouped together into virtual memories (VMs) based on certain rules, before being mapped onto the appropriate physical memories from the library, which allow the application to meet its area and performance constraints. Note that, since the focus of this paper is not on systemlevel energy reduction, we do not perform fine grain application level data reuse analysis to cluster frequently accessed data onto a smaller memory like in [47] and [48]. The grouping of data blocks (DBs) in our approach allows us to reduce the number of memories in the design, thus reducing area.…”

Section: Memory Subsystemmentioning

confidence: 99%