A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC

Pasricha, Sudeep; Dutt, Nikil

doi:10.1109/tcad.2006.884487

Cited by 20 publications

(12 citation statements)

References 46 publications

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“…An explorer with performance estimator is shown in Figure 2. Examples of such approaches are [4][5][6][7][8][9][10][11][12][13][14][15].…”

Section: Fig 1: Asip Design Methodologymentioning

confidence: 99%

ADA: Applications Define ASIP

Jain¹

2014

IJCA

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Interest in Application Specific Instruction set Processors or ASIPs has increased significantly. Sincere efforts have been put in improving ASIP design methodologies in industry as well as in academia. By the close observation and analysis of these approaches, it was found that though the existing approaches are focusing on making the process automatic and providing better GUI to help the designers, core technique used in deciding the suitable architecture (processor and memory) is based on design space exploration. This exploration is done with the help of estimators. Such estimators are either simulator based or scheduler based. This study identifies that both types of techniques are very far from the ideal dream technique in which applications should have defined the suitable architecture configuration and these techniques are becoming unsuitable in current scenario. Each problem has a solution hidden in it. This scenario motivated us to propose a novel and revolutionary ASIP design technique making the dream true. The Proposed technique does not focuses on design space exploration, it focuses on directly defining processors for given applications rather than searching for suitable configuration in a jungle of configurations can be suggested by the architecture design space. General TermsComputer Architecture, Processor Design, Processor Design Technology.

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“…An explorer with performance estimator is shown in Figure 2. Examples of such approaches are [4][5][6][7][8][9][10][11][12][13][14][15].…”

Section: Fig 1: Asip Design Methodologymentioning

confidence: 99%

ADA: Applications Define ASIP

Jain¹

2014

IJCA

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“…Mai et al [1] enable manual algorithm execution by largely simplifying the low power optimization problem. The authors of [5,8] target the combined optimization problem of memory and bus partitioning for multi-master, multi-memory systems. Zhuge et al [9] distribute variables between different memory instances to increase digital signal processor (DSP) performance.…”

Section: Related Workmentioning

confidence: 99%

“…Since up to 60 % of an embedded system's power consumption is attributed to memory [1], optimizing the memory subsystems is an evident design goal. A commonly used method to reduce memory power consumption is splitting memory into several individual memory instances [1][2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Low power memory allocation and mapping for area-constrained systems-on-chips

2016

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Large fractions of today's embedded systems' power consumption can be attributed to the memory subsystem. In order to reduce this fraction, we propose a mathematical model to optimize on-chip memory configurations for minimal power. We exploit the power reduction effect of splitting memory into subunits with frequently accessed addresses mapped to small memories. The definition of an integer linear programming model enables us to solve the twofold problem of allocating an optimal set of memory instances with varying size on the one hand and finding an optimal mapping of application segments to allocated memories on the other hand. Experimental results yield power reductions of up to 82 % for instruction memory and 73 % for data memory. Area usage, at the same time, deteriorates by only 2.1 %, respectively, 1.2 % on average and even improves in some cases. Flexibility and performance of our model make it a valuable tool for low power system-on-chip design, either for efficient design space exploration or as part of a HW/SW codesign synthesis flow.

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“…Hence, an oversimplified synthesis method might result in infeasible or suboptimal solutions only. Many approaches are heavily biased toward either computation synthesis (e.g., [15] and [16]) or communication synthesis (e.g., [17]- [19]), assuming the counterpart to be done by a different tool. In order to ensure feasibility and optimality, however, an ESL synthesis methodology should support computation and communication synthesis with all their respective subtasks.…”

Section: Esl Synthesismentioning

confidence: 99%

Electronic System-Level Synthesis Methodologies

Gerstlauer

Haubelt

Pimentel

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

140

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Abstract-With ever-increasing system complexities, all major semiconductor roadmaps have identified the need for moving to higher levels of abstraction in order to increase productivity in electronic system design. Most recently, many approaches and tools that claim to realize and support a design process at the so-called electronic system level (ESL) have emerged. However, faced with the vast complexity challenges, in most cases at best, only partial solutions are available. In this paper, we develop and propose a novel classification for ESL synthesis tools, and we will present six different academic approaches in this context. Based on these observations, we can identify such common principles and needs as they are leading toward and are ultimately required for a true ESL synthesis solution, covering the whole design process from specification to implementation for complete systems across hardware and software boundaries.

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A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC

Cited by 20 publications

References 46 publications

ADA: Applications Define ASIP

ADA: Applications Define ASIP

Low power memory allocation and mapping for area-constrained systems-on-chips

Electronic System-Level Synthesis Methodologies

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