Simultaneous information flow security and circuit redundancy in Boolean gates

Hu, Wei; Oberg, Jason; Mu, Dejun; Kastner, Ryan

doi:10.1145/2429384.2429511

Cited by 9 publications

(3 citation statements)

References 19 publications

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“…GLIFT [23] is a shadow-logic-based technique that adds logic to all the gates, resulting in design complexity and overhead. Data-flow logic [24] serves as a backbone, which is used in several proposed techniques, including [25][26][27], where optimized labeling and enhanced encoding techniques help to reduce complexity but affect the precision logic of the system. An asset-based GLIFT [28] model provides structural checking with security properties.…”

Section: Fine-grained Ift Modelsmentioning

confidence: 99%

Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V

Nicholas,

Aklekar,

Thakar

et al. 2023

Cryptography

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With the proliferation of electronic devices, third-party intellectual property (3PIP) integration in the supply chain of the semiconductor industry and untrusted actors/fields have raised hardware security concerns that enable potential attacks, such as unauthorized access to data, fault injection and privacy invasion. Different security techniques have been proposed to provide resilience to secure devices from potential vulnerabilities; however, no one technique can be applied as an overarching solution. We propose an integrated Information Flow Tracking (IFT) technique to enable runtime security to protect system integrity by tracking the flow of data from untrusted communication channels. Existing hardware-based IFT schemes are either fine-, which are resource-intensive, or coarse-grained models, which have minimal precision logic, providing either control-flow or data-flow integrity. No current security model provides multi-granularity due to the difficulty in balancing both the flexibility and hardware overheads at the same time. This study proposes a multi-level granularity IFT model that integrates a hardware-based IFT technique with a gate-level-based IFT (GLIFT) technique, along with flexibility, for better precision and assessments. Translation from the instruction level to the data level is based on module instantiation with security-critical data for accurate information flow behaviors without any false conservative flows. A simulation-based IFT model is demonstrated, which translates the architecture-specific extensions into a compiler-specific simulation model with toolchain extensions for Reduced Instruction Set Architecture (RISC-V) to verify the security extensions. This approach provides better precision logic by enhancing the tagged mechanism with 1-bit tags and implementing an optimized shadow logic that eliminates the area overhead by tracking the data for only security-critical modules.

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Section: Fine-grained Ift Modelsmentioning

confidence: 99%

Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V

Nicholas,

Aklekar,

Thakar

et al. 2023

Cryptography

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“…For example, logic redundancy has been used to achieve area and/or timing optimization in synchronous and asynchronous digital circuit designs [23], [24], and used to improve the yield of digital integrated circuit designs [25]. Reference [26] discusses a novel logic redundancy method called gate level information flow tracking, which consumes three times the area of the original circuit. Reference [27] also presented a new logic redundancy method called turtle logic, which primarily addresses the design of digital circuits to cope with noisy scenarios for operation under ultralow supply voltages (i.e.…”

Section: Introductionmentioning

confidence: 99%

Redundant logic insertion and fault tolerance improvement in combinational circuits

Balasubramanian

Naayagi

2017

2017 International Conference on Circuits, System and Simulation (ICCSS)

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Abstract-This paper presents a novel method to identify and insert redundant logic into a combinational circuit to improve its fault tolerance without having to replicate the entire circuit as is the case with conventional redundancy techniques. In this context, it is discussed how to estimate the fault masking capability of a combinational circuit using the truth-cum-fault enumeration table, and then it is shown how to identify the logic that can introduced to add redundancy into the original circuit without affecting its native functionality and with the aim of improving its fault tolerance though this would involve some trade-off in the design metrics. However, care should be taken while introducing redundant logic since redundant logic insertion may give rise to new internal nodes and faults on those may impact the fault tolerance of the resulting circuit. The combinational circuit that is considered and its redundant counterparts are all implemented in semi-custom design style using a 32/28nm CMOS digital cell library and their respective design metrics and fault tolerances are compared.

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“…Information flow security can be addressed from various abstraction levels of the system stack, including programming language, compiler, operating system (OS), instruction set architecture (ISA) or even down to the lowest level of Boolean gates. However, programming language level information flow tracking (IFT) methods force programmers to comply with new typing systems that lead to higher design complexity [12]. OS level IFT approaches build information flow control mechanisms into the OS and thus can take the pressure of high design complexity off programmers.…”

Section: Introductionmentioning

confidence: 99%