Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design

Atat, Youssef; Zergainoh, Nacer-Eddine

doi:10.1109/isvlsi.2007.90

Cited by 8 publications

(6 citation statements)

References 7 publications

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“…For example, in [6], [7], the authors use an IP block based design environment to generate SystemC based architecture specifications, starting from a netlist of functional modules described in MATLAB. A similar methodology is presented in [1] for multiprocessor system-on-chips (MPSoC) target architectures.…”

Section: High Level Synthesis Flowmentioning

confidence: 99%

“…The Host-FPGA interface block is composed of PCI interface controller that generates the control signals for the PCI Express interface core 1 and input/output buffer as shown in Figure 12. The PCI interface controller block supports DMA operations to maximize the communication speed using burst mode transactions.…”

Section: Host-fpga Interface Blockmentioning

confidence: 99%

“…The communication of data to and from the FPGA board is synchronized using interrupts. The input data is structured by the host 1. The PCI Express Endpoint LogiCORE from Xilinx is used for PCI Express Core.…”

Section: Tanor Software Modulesmentioning

confidence: 99%

“…In many applications, algorithms are subject to change making reconfigurability desirable [1], [2]. Recent advances in reconfigurable hardware, especially field programmable gate arrays (FPGAs), provide a new hardware alternative for designers that combines the versatility of FPGAs with the performance advantage of ASICs [3].…”

Section: Introductionmentioning

confidence: 99%

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An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization

Kim

Deng

Mangalagiri

et al. 2009

IEEE Trans. Comput.

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Abstract-This paper describes TANOR, an automated framework for designing hardware accelerators for numerical computation on reconfigurable platforms. Applications utilizing numerical algorithms on large-size data sets require high-throughput computation platforms. The focus is on N-body interaction problems which have a wide range of applications spanning from astrophysics to molecular dynamics. The TANOR design flow starts with a MATLAB description of a particular interaction function, its parameters, and certain architectural constraints specified through a graphical user interface. Subsequently, TANOR automatically generates a configuration bitstream for a target FPGA along with associated drivers and control software necessary to direct the application from a host PC. Architectural exploration is facilitated through support for fully custom fixed-point and floating point representations in addition to standard number representations such as single precision floating point. Moreover, TANOR enables joint exploration of algorithmic and architectural variations in realizing efficient hardware accelerators. TANOR's capabilities have been demonstrated for three different N-body interaction applications: the calculation of gravitational potential in astrophysics, the diffusion or convolution with Gaussian kernel common in image processing applications, and the force calculation with vector-valued kernel function in molecular dynamics simulation. Experimental results show that TANOR-generated hardware accelerators achieve lower resource utilization without compromising numerical accuracy, in comparison to other existing custom accelerators.

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Section: High Level Synthesis Flowmentioning

confidence: 99%

Section: Host-fpga Interface Blockmentioning

confidence: 99%

Section: Tanor Software Modulesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization

Kim

Deng

Mangalagiri

et al. 2009

IEEE Trans. Comput.

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“…However, DSP algorithm developers still prefer to use highlevel languages like C or MATLAB [2] to prototype and test their algorithms. One way of bridging the gap is to provide an easy mechanism for translating the high level algorithmic description onto an FPGA platform using parameterizable Intellectual Property (IP) cores [3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Accurate Area, Time and Power Models for FPGA-Based Implementations

Deng

Sobti

Zhang

et al. 2009

J Sign Process Syst

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This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family (Deng et al. 2008). These models are designed to facilitate efficient design space exploration in an automated algorithmarchitecture codesign framework. Detailed models for estimating the number of slices, block RAMs and 18 × 18-bit multipliers for fixed point and floating point IP cores have been developed. These models are also utilized to develop power models that consider the effect of logic power, signal power, clock power and I/O power. Timing models have been developed to predict the latency of the fixed point and floating point IP cores. In all cases, the model coefficients have been derived by using curve fitting or regression analysis. The modeling error is quite small for single IP cores; the error for the area estimate, for instance, is on the This paper is an extension of the ICASSP'08 paper "Accurate Models for Estimating Area and Power of FPGA Implementations". average 0.95%. The error for fairly large examples such as floating point implementation of 8-point FFTs is also quite small; it is 1.87% for estimation of number of slices and 3.48% for estimation of power consumption. The proposed models have also been integrated into a hardware-software partitioning tool to facilitate design space exploration under area and time constraints.

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