International audienceThe variety of wireless communication standards and their corresponding applications requires more and more flexible, yet efficient, implementations. The emerging flexibility need induces a new challenge when added to the ever increasing requirements in terms of high throughput and low complexity. This paper presents a design of an application-specific processor dedicated for a minimum mean square error interference cancellation (MMSE-IC) linear equalizer (LE) used in iterative multi-input multi-output (MIMO) turbo receiver. The explored design approach applies static scheduling of datapath control signals. The proposed architecture supports the requirements of flexibility for different MIMO system configurations concerning channel time selectivity and transmission diversity. In order to evaluate the efficiency of the adopted architecture model for this kind of applications and requirements, a fair comparison is conducted with a state-of-the-art application specific instruction-set processor (ASIP) implementation. The obtained results illustrate a significant performance improvement in terms of execution time and implementation area while using identical computational resources and supporting same flexibility parameters
ISBN: 0-7695-2896-1International audienceThe rise of the abstraction level when designing the hardware (HW) and software (SW) parts of multiprocessor systems on chip (MPSoC) permits to master the growing complexity of these systems. However, it generates a huge gap between the concepts of system level specification and those used for implementation and synthesis of HW/SW MPSoC. This paper deals with the system level design for rapid prototyping of MPSoC starting from Matlab/Simulink specification. We propose a new approach to establish a bridge between the system level specification and the HW/SW architecture at the implementation level
Applications in wireless digital communication field are becoming increasingly complex and diverse. Circuits and systems adopted in this application domain must not only consider performance and implementation constraints, but also the requirement of flexibility. The combination of flexibility and the ever increasing performance requirements demands design approach that provides better ways of controlling and managing hardware resources. Application Specific Instruction-set Processor (ASIP) design approach is key trend in designing flexible architectures. The ASIP concept implies dynamic scheduling of a set of instructions which generally leads to an overhead related to instruction decoding. No-Instruction-Set-Computer (NISC) concept has been introduced to reduce this overhead through the adoption of static scheduling. In this paper, the NISC approach is explored through a casestudy design of universal demapper for multiple wireless standards. The proposed design has common main architectural choices as a state-ofthe-art ASIP for comparison purpose. The obtained results illustrate a significant improvement in execution time and implementation area while using identical computational resources and supporting same flexibility parameters.
In the domain of digital wireless communication, flexible design implementations are increasingly explored for different applications in order to cope with diverse system configurations imposed by the emerging wireless communication standards. In fact, shrinking the design time to meet market pressure, on the one hand, and adding the emerging flexibility requirement and, hence, increasing system complexity, on the other hand, require a productive design approach that also ensures final design quality. The no instruction set computer (NISC) approach fulfills these design requirements by eliminating the instruction set overhead. The approach offers static scheduling of the datapath, automated register transfer language (RTL)synthesis and allows the designer to have direct control of hardware resources. This paper presents a complete NISC-based design and prototype flow, from architecture specification till FPGA implementation. The proposed design and prototype flow is illustrated through two case studies of flexible implementations, which are dedicated to low-complexity MIMO turbo-equalizer and a universal turbo-demapper. Moreover, the flexibility of the proposed prototypes allows supporting all communication modes defined in the emerging wireless communication standards, such LTE, LTE-Advanced, WiMAX, WiFi and DVB-RCS. For each prototype, its functionality is evaluated, and the resultant performance is verified for all system configurations.
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