Accurate Area, Time and Power Models for FPGA-Based Implementations

Abstract

This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family (Deng et al. 2008). These models are designed to facilitate efficient design space exploration in an automated algorithmarchitecture codesign framework. Detailed models for estimating the number of slices, block RAMs and 18 × 18-bit multipliers for fixed point and floating point IP cores have been developed. These models are also utilized to develop power models that consider the effect of logic power, signal power, clock power and I/O power. Timing models have been developed to predict the latency of the fixed point and floating point IP cores. In all cases, the model coefficients have been derived by using curve fitting or regression analysis. The modeling error is quite small for single IP cores; the error for the area estimate, for instance, is on the This paper is an extension of the ICASSP'08 paper "Accurate Models for Estimating Area and Power of FPGA Implementations". average 0.95%. The error for fairly large examples such as floating point implementation of 8-point FFTs is also quite small; it is 1.87% for estimation of number of slices and 3.48% for estimation of power consumption. The proposed models have also been integrated into a hardware-software partitioning tool to facilitate design space exploration under area and time constraints.

Type-Driven Automated Program Transformations and Cost Modelling for Optimising Streaming Programs on FPGAs

“…Figure 8 shows the result of comparison against Altera-OpenCL (AOCL), using a 2D SOR kernel. 10 The Tytra solution (with an AOCL shell) yields an order of magnitude better performance than the AOCL-only solution on the same FPGA.…”

“…However, their work focuses on loop-unrolling, and is fundamentally different in terms of design entry and variant generation. Deng et al [10] present cost models based on the MATLAB-based FANTOM tool, for area, time and power. Their estimation model works on generated HDL whereas we make estimates at a higher abstraction, and our approach of generating and evaluating variants is fundamentally different.…”

Efficient AFT implementation in FPGAs to detect potential electromigration failures

“…The a n coefficient can be calculated by α =0 and b n coefficient can be calculated by α= (1/4n). Prasanna et al [5] showed that using Bruns original form, the even and odd Fourier coefficients can be computed by equations (7) and (8).Therefore, The Bruns original AFT uses the weighted s discrete values of A(t) where the weights w given as ± 1. An improved and area effici design of AFT is implemented on Xilinx Vir data flow for AFT implementation is shown in…”

“…Although the de coefficients using the proposed meth impact on the system performance the AFT algorithm onto Xilinx FPG first computed. In order to validate also computed in Matlab using direc (7) and (8).…”

Design of Mobile DDR IO Standards Based Portable Devnagari Unicode Reader on FPGA

“…The power phase measurement system is designed based on FPGA, and the results indicate it almost immune to noise of power [8]. Reference [9] develop power models that consider the effect of logic power, signal power, clock power and I/O power. With the development of technology and usage of FPGA, the power quality detect devices become more and more powerful and the measure accuracy increase quickly [10].…”