Simulation of defect detection schemes for wafer inspection in VLSI manufacturing

Swecker, Aaron L.; Strojwas, Andrzej J.; Li, Xiaolei; Levy, Ady

doi:10.1109/sispad.1997.621358

Cited by 2 publications

(1 citation statement)

References 5 publications

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“…Some scalar 2-D simulators such as SPLAT 5 and SAMPLE 6 run very fast but are only valid provided that the feature size is much larger than the illumination wavelength and dielectric layer is much thinner than the wavelength 1 . 4 . This research has laid the foundation for our work.…”

Section: Simulation Approachmentioning

confidence: 99%

Three-dimensional modeling of wafer inspection schemes for sub-70-nm lithography

2002

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The production of 70nm devices is projected for the year 2008. With this projection, optical lithography will become more challenging since as the device size goes down, the potential for introducing killer defects also increases dramatically. Wafer inspection will play a key role in controlling the defect mechanisms and keeping an acceptable yield for next generation VLSI manufacturing.Metrology tools for the new generation lithography will have the following features. First, the projection and collection lenses will have higher numerical apertures (NA) to obtain high-resolution images. Typically, the NA will be as high as 0.9. Second, the wavelength used for wafer inspection will be much smaller so that common wafer materials will become highly absorptive. Last, with the increased number of process steps, wafer inspection will need to provide information for more critical processes. Based on these features, accurate modeling of the next generation wafer inspection schemes is needed to aid in the characterization and optimization of the inspection tools. The simulation tool must be able to simulate inspection systems with high NA lens, DUV wavelengths, and highly absorptive wafer materials accurately and quickly.At Carnegie Mellon University, a simulator called METRO-3D was developed into a defect inspection simulator for DUV lithography processes. This simulator is able to successfully model various types of defect mechanisms. However, it has experienced occasional numerical instabilities, with discontinuous dielectric structures composed of highly absorptive materials. In order to provide a tool to simulate the wafer inspection scheme of SUB-70NM NODE LITHOGRAPHY, we have incorporated a new algorithm to model the wafer inspection system more accurately and robustly. Numerical experiments shows that the algorithm is capable of simulating topographies with discontinuous dielectric functions, yielding stable results even when the material is highly absorptive.To verify the accuracy of the simulator, several simulations were compared with both analytical models and results form other existing simulators (e.g. Gsolver and METRO-2D). The results show good matches between METRO-3D and these well-established results. Finally, we performed simulations on industrial data and the results exemplified the ability of METRO-3D to model complex 3-D structures. In this paper we will present is efficient and stable EM solver and the results of the simulator applied to various sub-70nm node wafer inspection schemes.

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Section: Simulation Approachmentioning

confidence: 99%

Three-dimensional modeling of wafer inspection schemes for sub-70-nm lithography

2002

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METRO-3D: an efficient three-dimensional wafer inspection simulator for next generation lithography

Zhu

Swecker

Strojwas

13th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference. Advancing the Science and Technology of Semiconductor Ma

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Wafer inspection schemes for next generation lithography (NGL) will play a key role in controlling defect mechanisms and maintaining an acceptable yield. Developing these wafer inspection schemes will require characterization and optimization of DUV wavelength illumination at high numerical apertures (greater than 0.9) to detect defects that may be a fraction of Ihe design rule. Using wafer inspection test benches that provide the flexibility for various illumination polarizations, numerical apertures, scanning or fidl field schemes can be extremely costly and therefore simulation of these schemes is necessary to characterize the various detection parameters. To model defects for NGL, three-dimensional simulation tools will be required to simulate highly absorptive material in the environment of shorter wavelength illumination. Also, the simulator will be required to simulate high numerical aperture (NA) inspection schemes to capture small defects. With the development of METRO-3D, a three-dimensional simulation tool that rigorously solves the EM field on arbitrary wafer topographies, we are able to model and characterize the wafer inspection schemes for NGL. In this paper, we will present simulation results from METRO-3D for various wafer inspection schemes, including high numerical aperture schemes, on NGL topographies with highly absorptive materials.

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Simulation of defect detection schemes for wafer inspection in VLSI manufacturing

Cited by 2 publications

References 5 publications

Three-dimensional modeling of wafer inspection schemes for sub-70-nm lithography

Three-dimensional modeling of wafer inspection schemes for sub-70-nm lithography

METRO-3D: an efficient three-dimensional wafer inspection simulator for next generation lithography

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