We have extended the capability of a vector 3D lithography simulator METROPOLE-3D from a photomask simulator to become a full 3D photolithography simulator. It is designed to run moderately fast on conventional engineering workstations. METROPOLE-3D solves Maxwell's equations rigorously in three dimensions to model how non-vertically incident light is scattered and transmitted in non-planar structures. METROPOLE-3D consists of several simulation modules: photomask simulator which models the aerial image of any mask pattern (including phase-shifting masks); exposure simulator which models light intensity distribution within the photoresist and arbitrary underlying non-planar substrate structures; postexposure baking module which models the photo-active compound diffusion, chemically amplified (CA) photoresist crosslinking and de-protection processes; and finally, 3D development module which models the photoresist development process using the level-set algorithm. This simulator has a wide range of applications in studying the pressing engineering problems encountered in state-of-the-art VLSI fabrication processes. The simulator has been applied to the layout printability! manufacturability analysis to study the dominant physical phenomena in lithography, deposition, CMP and etching processes that affect the transfer of mask patterns to the final etched structures on the wafers. Using this new 3D rigorous photolithography simulator, optical proximity effects have been studied. A reflective notching problem caused by the reflective substrate structure has been thoroughly studied, and an anti-reflective coating (ARC) solution to this notching problem has been optimized by the simulations. Finally, a 3D contamination to defect transformation study was successfully performed using our rigorous simulator.
Particulate contamination deposited on silicon wafers is typically the dominant reason for yield loss in VLSI manufacturing. The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the defect location, size, material and the underlying IC topography. A rigorous topography simulator, METROPOLE, has been developed to allow the prediction and correlation of the critical physical parameters (material, size and location) of contamination in the manufacturing process to device defects. The results for a large number of defect samples simulated using the above approach were compared with data gathered from the AMD-Sunnyvale fabline. A good match was obtained indicating the accuracy of this method which provided a framework for developing contamination to defect propagation/growth macromodels. We have demonstrated that the understanding of defect transformation can be applied to early yield impact prediction.
The production of 70nm devices is projected for the year 2008. With this projection, optical lithography will become more challenging since as the device size goes down, the potential for introducing killer defects also increases dramatically. Wafer inspection will play a key role in controlling the defect mechanisms and keeping an acceptable yield for next generation VLSI manufacturing.Metrology tools for the new generation lithography will have the following features. First, the projection and collection lenses will have higher numerical apertures (NA) to obtain high-resolution images. Typically, the NA will be as high as 0.9. Second, the wavelength used for wafer inspection will be much smaller so that common wafer materials will become highly absorptive. Last, with the increased number of process steps, wafer inspection will need to provide information for more critical processes. Based on these features, accurate modeling of the next generation wafer inspection schemes is needed to aid in the characterization and optimization of the inspection tools. The simulation tool must be able to simulate inspection systems with high NA lens, DUV wavelengths, and highly absorptive wafer materials accurately and quickly.At Carnegie Mellon University, a simulator called METRO-3D was developed into a defect inspection simulator for DUV lithography processes. This simulator is able to successfully model various types of defect mechanisms. However, it has experienced occasional numerical instabilities, with discontinuous dielectric structures composed of highly absorptive materials. In order to provide a tool to simulate the wafer inspection scheme of SUB-70NM NODE LITHOGRAPHY, we have incorporated a new algorithm to model the wafer inspection system more accurately and robustly. Numerical experiments shows that the algorithm is capable of simulating topographies with discontinuous dielectric functions, yielding stable results even when the material is highly absorptive.To verify the accuracy of the simulator, several simulations were compared with both analytical models and results form other existing simulators (e.g. Gsolver and METRO-2D). The results show good matches between METRO-3D and these well-established results. Finally, we performed simulations on industrial data and the results exemplified the ability of METRO-3D to model complex 3-D structures. In this paper we will present is efficient and stable EM solver and the results of the simulator applied to various sub-70nm node wafer inspection schemes.
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