Simulation experiments of a high-performance RapidIO-based processing architecture

Adams, John; Katsinis, C.; Rosen, Warren A.; Hecht, D.; Adams, V.; Narravula, H.; Sukhtankar, S.; Lachenmaier, R.

doi:10.1109/nca.2001.962550

Cited by 5 publications

(3 citation statements)

References 1 publication

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“…The optical interface protocol is Serial Rapid IO (SRIO), which is the main interface for accessing the Gradient Amplifier.The RapidIO has Up to 10 Gb/s of bandwidth, low latency and low power which increases the performance of rapid developing communication technologies. This protocol comprise a highly flexible and optimized Physical, logical and transport layer [8] Software control communication. This interface also used for sending digital current setpoints to MOD X, Y and Z.…”

Section: B Serial Rapid Io Communication Protocolmentioning

confidence: 99%

Serial Rapid IO high speed optical interface protocol for Indigenous MRI

Dipnaik¹,

Ukey²,

Patel³

et al. 2020

AJCT

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This paper presents the available literature on high speed Serial Rapid Input Output communication protocol. The MRI gradient amplifier system consists of a cabinet with a power supply and three Gradient Amplifiers. It is a three axes Gradient Amplifier system, which can be used in a MRI system to control the X, Y and Z Gradient Coils. The optical interface this current setpoint can be transmitted digitally to the Gradient Amplifier. The gradient amplifier system possess optical interface which is a high speed interface intended for communication of current setpints, system clock, control diagnostics by the MRI system host. This optical interface benefits from digital optical isolation and removes cable, conversion loses and noise on the current setpoint.

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Section: B Serial Rapid Io Communication Protocolmentioning

confidence: 99%

Serial Rapid IO high speed optical interface protocol for Indigenous MRI

Dipnaik¹,

Ukey²,

Patel³

et al. 2020

AJCT

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show abstract

“…Adams et al [14] have done a simulation analysis of a high-performance processing architecture based on RapidIO. Two network topologies were simulated: a simple network consisting of an 8-port switch and 8 processing nodes and a more extensive network consisting of five 8-port switches and 24 processing nodes.…”

Section: Related Workmentioning

confidence: 99%

Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect

Klilou

Belkouch

Elleaume

et al. 2014

EURASIP J. Adv. Signal Process.

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Pulse-Doppler radars require high-computing power. A massively parallel machine has been developed in this paper to implement a Pulse-Doppler radar signal processing chain in real-time fashion. The proposed machine consists of two C6678 digital signal processors (DSPs), each with eight DSP cores, interconnected with Serial RapidIO (SRIO) bus. In this study, each individual core is considered as the basic processing element; hence, the proposed parallel machine contains 16 processing elements. A straightforward model has been adopted to distribute the Pulse-Doppler radar signal processing chain. This model provides low latency, but communication inefficiency limits system performance. This paper proposes several optimizations that greatly reduce the inter-processor communication in a straightforward model and improves the parallel efficiency of the system. A use case of the Pulse-Doppler radar signal processing chain has been used to illustrate and validate the concept of the proposed mapping model. Experimental results show that the parallel efficiency of the proposed parallel machine is about 90%.

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“…It has been conceived as a technology targeted at processor-toprocessor and board-to-board interconnection in embedded systems [1]. It supports all needed microprocessor and I/O transactions, and is transparent to existing applications and operation system software [2]. It is built upon Low Voltage Different Signaling standard for high speed and low power dissipation.…”

Section: Introductionmentioning

confidence: 99%

Design of RapidIO logical core based on safety arbitration mechanisms

Fengfeng

Song

Yang

et al. 2010

2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)

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RapidIO is an emerging high-performance and pointto-point packetized interconnection technology. In this paper, the design of the logical core based on safety arbitration mechanisms is described in detail. The packing and unpacking of I/O Logical, Message Passing and Globally Shared Memory transactions are achieved. Excellent average data transfer rates, up to 7.8 bytes per cycle are reached in certain transactions with 256-byte data payloads, meanwhile the data efficiencies are more than 95%. Moreover, maintenance read transactions targeted at local capability and status registers can be executed in a lower latency compared with the reference design.

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Simulation experiments of a high-performance RapidIO-based processing architecture

Cited by 5 publications

References 1 publication

Serial Rapid IO high speed optical interface protocol for Indigenous MRI

Serial Rapid IO high speed optical interface protocol for Indigenous MRI

Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect

Design of RapidIO logical core based on safety arbitration mechanisms

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