Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect

Klilou, Abdessamad; Belkouch, Saïd; Elleaume, Philippe; Gall, Philippe; Bourzeix, François; Hassani, Moha M’Rabet

doi:10.1186/1687-6180-2014-161

Cited by 19 publications

(11 citation statements)

References 21 publications

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“…This makes it possible for use in several computeintensive applications, such as radar processing [41]. Our work has been used within the official FFT library of Texas Instruments [42].…”

Section: Implementation and Experimental Resultsmentioning

confidence: 99%

Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage

Bahtat

Belkouch

Elleaume

et al. 2016

EURASIP J. Adv. Signal Process.

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The fast Fourier transform (FFT) is perhaps today's most ubiquitous algorithm used with digital data; hence, it is still being studied extensively. Besides the benefit of reducing the arithmetic count in the FFT algorithm, memory references and scheme's projection on processor's architecture are critical for a fast and efficient implementation. One of the main bottlenecks is in the long latency memory accesses to butterflies' legs and in the redundant references to twiddle factors. In this paper, we describe a new FFT implementation on high-end very long instruction word (VLIW) digital signal processors (DSP), which presents improved performance in terms of clock cycles due to the resulting low-level resource balance and to the reduced memory accesses of twiddle factors. The method introduces a tradeoff parameter between accuracy and speed. Additionally, we suggest a cache-efficient implementation methodology for the FFT, dependently on the provided VLIW hardware resources and cache structure. Experimental results on a TI VLIW DSP show that our method reduces the number of clock cycles by an average of 51 % (2 times acceleration) when compared to the most assembly-optimized and vendor-tuned FFT libraries. The FFT was generated using an instruction-level scheduling heuristic. It is a modulo-based register-sensitive scheduling algorithm, which is able to compute an aggressively efficient sequence of VLIW instructions for the FFT, maximizing the parallelism rate and minimizing clock cycles and register usage.

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“…This makes it possible for use in several computeintensive applications, such as radar processing [41]. Our work has been used within the official FFT library of Texas Instruments [42].…”

Section: Implementation and Experimental Resultsmentioning

confidence: 99%

Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage

Bahtat

Belkouch

Elleaume

et al. 2016

EURASIP J. Adv. Signal Process.

Self Cite

View full text Add to dashboard Cite

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“…We usually use parallel computing method to solve the real-time performance problem when faced with large computation burden in the field of image processing [3], audio processing [4], radar signal processing [5], etc. The common characteristic of these fields is that they need to deal with lots of data in short time, and parallel computing in these problems is to parallelize the matrix computing.…”

Section: Introductionmentioning

confidence: 99%

Parallel Computing Method for the Non-linear Model of Displacement Measurement

Chai

Chen

et al. 2015

Proceedings of the 2015 International Conference on Test, Measurement and Computational Methods

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Non-linear model of displacement and sensor detection is usually used in multi-DOF precise displacement measurement. The computing burden of these models is often too large to satisfy the need of real-time performance of displacement measurement. This paper proposes a parallel computing method based on the task scheduling model, and uses GA to optimize task scheduling plan to enhance the real-time performance of displacement measurement.

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“…Again, hardware-verified performance in FLOPS linearly increases with the number of DSP cores. As the output of the pulse compression is arranged along the range gate dimension, the output needs to undergo a corner turn before being handled by the Doppler filtering processors [23]. This two-dimensional corner turn operation is equivalent to a matrix transpose in the memory space.…”

Section: Doppler Processing and Corner Turnmentioning

confidence: 99%

An Implementation of Real-Time Phased Array Radar Fundamental Functions on DSP-Focused, High-Performance Embedded Computing Platform

Zhang

Patel

et al. 2016

Preprint

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This paper investigates the feasibility of a backend design for real-time, multiple-channel processing digital phased array system, particularly for high-performance embedded computing platforms constructed of using general purpose digital signal processors. Frist, we obtained the labscale backend performance benchmark from simulating beamforming, pulse compression, and Doppler filtering based on MicroTCA chassis using Serial RapidIO protocol in backplane communication. Next, a field-scale demonstrator of a multifunctional phased array radar is emulated by using the similar configuration. Interestingly, the performance of a barebone design is compared to that of emerging tools that systematically take advantage of parallelism and multicore capabilities, including Open Computing Language.

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Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect

Cited by 19 publications

References 21 publications

Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage

Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage

Parallel Computing Method for the Non-linear Model of Displacement Measurement

An Implementation of Real-Time Phased Array Radar Fundamental Functions on DSP-Focused, High-Performance Embedded Computing Platform

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