Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage

Abstract

The fast Fourier transform (FFT) is perhaps today's most ubiquitous algorithm used with digital data; hence, it is still being studied extensively. Besides the benefit of reducing the arithmetic count in the FFT algorithm, memory references and scheme's projection on processor's architecture are critical for a fast and efficient implementation. One of the main bottlenecks is in the long latency memory accesses to butterflies' legs and in the redundant references to twiddle factors. In this paper, we describe a new FFT implementation on high-end very long instruction word (VLIW) digital signal processors (DSP), which presents improved performance in terms of clock cycles due to the resulting low-level resource balance and to the reduced memory accesses of twiddle factors. The method introduces a tradeoff parameter between accuracy and speed. Additionally, we suggest a cache-efficient implementation methodology for the FFT, dependently on the provided VLIW hardware resources and cache structure. Experimental results on a TI VLIW DSP show that our method reduces the number of clock cycles by an average of 51 % (2 times acceleration) when compared to the most assembly-optimized and vendor-tuned FFT libraries. The FFT was generated using an instruction-level scheduling heuristic. It is a modulo-based register-sensitive scheduling algorithm, which is able to compute an aggressively efficient sequence of VLIW instructions for the FFT, maximizing the parallelism rate and minimizing clock cycles and register usage.

High-Throughput Polynomial Multiplier Architecture for Lattice-Based Cryptography

“…However, thanks to pipelining, the CPPR2B of our design is very close to 1 when performing NTT incessantly. When four NTTs are performed successively, CPPR2B of our design is 1.27, which is better than the 1.4 of the VLIW processor [21]. Our design has an advantage in applications which need to perform NTT successively, such as CRYSTALS-Dilithium.…”

“…Bahtat proposed the efficient scheduling way for FFT in VLIW processors [21], and measured his design by the number of cycles per pseudo radix-2 butterfly(CPPR2B). In our 2stream design, Thus, the proposed design focuses on throughput instead of latency as compared to the previous designs.…”

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“…The second line of research focused on task scheduling within the conventional FFT implementations to speed up computation over specialized hardware. For example, [14] improved the butterfly task scheduling in a very-long-instructionword (VLIW) digital signal processors (DSP) chip using a software pipelining technique called modulo scheduling. This scheduling algorithm exploits the instruction-level parallelism (ILP) feature in the VLIW DSP platform to schedule multiple loop iterations in an overlapping manner [15].…”

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“…Moreover, it provides a maximum performance of 128 GFLOPS for a single precision floating point calculation [4]. In addition, several research communities have developed high-performance computing systems using the C6678 DSP [3,[5][6][7][8][9].…”