Design of RapidIO logical core based on safety arbitration mechanisms

Abstract

RapidIO is an emerging high-performance and pointto-point packetized interconnection technology. In this paper, the design of the logical core based on safety arbitration mechanisms is described in detail. The packing and unpacking of I/O Logical, Message Passing and Globally Shared Memory transactions are achieved. Excellent average data transfer rates, up to 7.8 bytes per cycle are reached in certain transactions with 256-byte data payloads, meanwhile the data efficiencies are more than 95%. Moreover, maintenance read transactions targeted at local capability and status registers can be executed in a lower latency compared with the reference design.