Simulation environment for a vision-system-on-chip with integrated processing

Abstract

Imagers with programmable, highly parallel signal processing execute computationally intensive processing steps directly on the sensor, thereby allowing early reduction of the amount of data to relevant features. For the purposes of architectural exploration during development of a novel Vision-System-on-Chip (VSoC), it has been modelled on system level. Aside from the integrated control unit with multiple independent control flows, the model also realizes digital and analogue signal processing. Due to high simulation speed and compatibility with the real system, especially regarding the programs to be executed, the resulting simulation model is very well suited for usage during application development. By providing the ability to purposefully introduce parameter deviations or defects at various points of analogue processing, it becomes possible to study them with respect to their influence on image processing algorithms executed within the VSoC

Review: tomographic imaging flow cytometry

“…[83][84][85] Another approach is the use of field-programmable gate arrays (FPGAs) [86][87][88] or vision system on chip (VSoC) sensors. 89,90 Here, a large part of the pre-processing of the image data is done close to the sensor and only the important data is transmitted to the controlling computer.…”

Hardware-aware performance evaluation for the co-design of image sensors and vision algorithms

“…An alternative approach is to explore the interdependences between elements at the different levels of the hierarchy, in order to find optimal combinations. For this to be implemented, the optimization loop must incorporate a detailed, yet manageable, description of the system [6]. That includes parameters describing the algorithm performance and, at the same time, an accurate account of the implementation nonidealities.…”