Simulation aided hardening of N-channel power MOSFETs to prevent single event burnout

IEEE Trans. Power Electron.

Zhang

Cao

et al. 2014

This paper investigates the single-event burnout (SEB) simulation results for both the standard and hardened structure of power U-shape gate MOSFETs (UMOSFETs). The Schottky source is proposed to reduce the work of the parasitic bipolar transistor inherent to the device. The hardened structure of power UMOSFETs with the Schottky source and N buffer layer is given, which can work normally and improve the SEB performance effectively. Both 70-and 120-V power MOSFETs are simulated and discussed in this paper. The SEB threshold voltages are increased to more than 94 percent of the breakdown voltages for both 70-and 120-V hardened structure, compared to 54 percent for standard power UMOSFETs.Index Terms-Hardened structure, power UMOSFET, Schottky source, single-event burnout (SEB).

Section: Introductionsupporting

confidence: 87%

“…It has been proved that p+ plug enlargement is an effective way to improve the SEB performance [7]. There are also many other parameters which can affect the occurrence of SEB such as carrier lifetime reduction and emitter doping decrease [8].…”

Section: Introductionmentioning

confidence: 99%

Single-Event Burnout Hardened Structure of Power UMOSFETs With Schottky Source

IEEE Trans. Power Electron.

Zhang

Cao

et al. 2014

“…It is located in the intercellular region right next to the channel. This position was found by different experimental studies and numerical simulations to be among the most sensitive positions to SEB [9], [10], [14]- [16]. In addition, the choice of this position for the charge generation allows one to simulate only half of a VDMOS cell, since the influence of the adjacent half cell can be considered to be negligible.…”

Section: Simulation Tool and Test Vehicle Descriptionsmentioning

confidence: 97%

Sensitive Volume and Triggering Criteria of SEB in Classic Planar VDMOS

Luu

Austin

Miller

et al. 2010

IEEE Trans. Nucl. Sci.

“…It is demonstrated that the p+ plug enlargement can make the device less sensitive to SEB [5]- [7]. Simulation and experimental results confirm that the addition of a buffer layer does indeed improve the device's SEB threshold voltage, thus, improving the device's SEB performance [8].…”

Section: Introductionmentioning

confidence: 81%

“…The aim of this paper is to harden the structure of the power UMOSFETs with design modifications [5]. The solutions simply modify the geometry of the p + plug, maintaining though the initial functionality of the device (it is verified that BV, V th , R DSon , and I-V characteristics are unchanged).…”

Section: B Modification Of the P + Plug Geometrymentioning

confidence: 99%

Single-Event Burnout Hardening of Power UMOSFETs With Optimized Structure

Zhang

IEEE Trans. Electron Devices

et al. 2013

This paper gives and explains the simulation results of single-event burnout (SEB) hardening in a power metaloxide semiconductor field-effect transistor U-Shape Metal Oxide Semiconductor Field Effect Transistor (trench-gate MOSFET). It includes p + plug enlargement and adds a buffer layer that is between the epitaxial layer and substrate. These two hardening solutions are compared and the optimized structure that can prevent SEB is given. The single event gate-rupture (SEGR) threshold voltages in different linear energy transfers are also compared with SEB results. In addition, the simulation results show that the change of gate bias can influence the occurrence of SEGR, and the natural radiation environment at cryogenic temperatures is also considered.Index Terms-Cryogenic temperature, gate bias, linear energy transfers (LET), power metal-oxide semiconductor fieldeffect transistor (UMOSFET), single-event burnout (SEB), SEB hardening.