Simple embedded NVM cell for PMIC applications

Abstract

An embedded non-volatile memory cell solution with a top-floatinggate structure for power management integrated circuit applications is presented. The cell is fabricated by high-voltage CMOS process (20 V) with low-voltage CMOS devices (5 V) and a PIP capacitor, without additional processing steps or extra photomasks. The fabricated cell shows stable endurance characteristics up to 10 3 cycles. The charge retention at 858C is less than 0.5 V after 10 3 cycles stress.Introduction: Recently, power management integrated circuits (PMICs) with non-volatile memory (NVM) cells have been widely reported by semiconductor manufacturers [1][2][3]. When combining PMICs with an NVM cell, process complexity is one of the major concerns because several different devices are embedded in a wafer, such as low-voltage MOSFETs, high-voltage MOSFETs, resistors, capacitors, inductors etc. Up to now, several NVM cell structures have been considered for embedded NVM in PMICs. Stacked-gate EEPROMs with doublelayered poly-Si [1] and silicon-oxide-nitride-oxide-silicon (SONOS) [2] have been proposed as a high-density application. To implement those cells into PMICs, extra masks and additional processing steps are unavoidable. Single poly-Si EEPROM (SPEE) cells have also been considered [3]. However, SPEE is only suitable for low-density applications due to large cell size. Note that the SPEE cell has two or more devices in a single unit cell and needs space between them. Hong and Hsue suggested a novel top-floating-gate (TFG) EEPROM structure for embedded NVM applications [4]. The TFG cell was demonstrated in 1.5 mm CMOS process with some process modifications [5]. In this Letter, we present experimental results of an embedded TFG cell for PMIC applications. The embedded TFG NVM cell is fabricated using 0.35 mm 20 V class high-voltage (HV) CMOS technology, which includes 5 V low-voltage (LV) CMOS and a poly-insulator-poly (PIP) capacitor process module.