A new analogue circuit design methodology using independently optimised self-cascode (SC) structures is proposed. Based on the concept of the dual-workfunction-gate structures, which are equivalent to SC structures, transconductance and output resistance optimised SC MOSFETs were used in the differential input and output stages, respectively. An operational amplifier (opamp) with the proposed design methodology using standard 0.18 µm CMOS technology was designed to provide better performance. The measured DC gain of the fabricated opamp with independently-optimised SC MOSFETs was approximately 12 dB higher than that of the conventional opamp.
A high-voltage extended drain MOS (EDMOS) transistor with a dual work function gate (DWFG) is discussed. This device enhances device performance by modifying the electric field in the channel. For DWFG EDMOS device fabrication, the polycrystalline silicon gates on the source and drain sides are doped by p + and n + ion implantation, respectively. Experimental results from the fabricated DWFG EDMOS devices show improved transconductance (g m), drain conductance (g ds) and specific on-resistance (R ON) characteristics without breakdown voltage reduction.
An embedded non-volatile memory cell solution with a top-floatinggate structure for power management integrated circuit applications is presented. The cell is fabricated by high-voltage CMOS process (20 V) with low-voltage CMOS devices (5 V) and a PIP capacitor, without additional processing steps or extra photomasks. The fabricated cell shows stable endurance characteristics up to 10 3 cycles. The charge retention at 858C is less than 0.5 V after 10 3 cycles stress.Introduction: Recently, power management integrated circuits (PMICs) with non-volatile memory (NVM) cells have been widely reported by semiconductor manufacturers [1][2][3]. When combining PMICs with an NVM cell, process complexity is one of the major concerns because several different devices are embedded in a wafer, such as low-voltage MOSFETs, high-voltage MOSFETs, resistors, capacitors, inductors etc. Up to now, several NVM cell structures have been considered for embedded NVM in PMICs. Stacked-gate EEPROMs with doublelayered poly-Si [1] and silicon-oxide-nitride-oxide-silicon (SONOS) [2] have been proposed as a high-density application. To implement those cells into PMICs, extra masks and additional processing steps are unavoidable. Single poly-Si EEPROM (SPEE) cells have also been considered [3]. However, SPEE is only suitable for low-density applications due to large cell size. Note that the SPEE cell has two or more devices in a single unit cell and needs space between them. Hong and Hsue suggested a novel top-floating-gate (TFG) EEPROM structure for embedded NVM applications [4]. The TFG cell was demonstrated in 1.5 mm CMOS process with some process modifications [5]. In this Letter, we present experimental results of an embedded TFG cell for PMIC applications. The embedded TFG NVM cell is fabricated using 0.35 mm 20 V class high-voltage (HV) CMOS technology, which includes 5 V low-voltage (LV) CMOS and a poly-insulator-poly (PIP) capacitor process module.
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