Silicon speedpath measurement and feedback into EDA flows

Killpack, Kip; Kashyap, Chandramouli; Chiprout, Eli

doi:10.1145/1278480.1278581

Cited by 31 publications

(6 citation statements)

References 8 publications

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“…Figure 1 shows the overall view of our methodology. At the post-silicon stage, the correct timing behavior of a circuit is validated by applying test vectors to the chip while clock shrinking is performed [10]. In Figure 1, this step is performed in a testbench environment.…”

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confidence: 99%

Debug Automation for Logic Circuits Under Timing Variations

Dehbashi

Fey

2013

IEEE Des. Test

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h DEBUGGING OF SPEED-LIMITING paths (speedpaths) is a key challenge in development of very large scale integrated (VLSI) circuits as timing variations induced by process and environmental effects are increasing. This paper presents an approach to automate speedpath debugging under timing variations. First, timing behavior of a circuit and corresponding variation models are converted into a functional domain. Then, our automated debugging based on boolean satisfiability (SAT) diagnoses speedpaths. The experimental results show the effectiveness of our approach on ISCAS'85 and ISCAS'89 benchmarks suites.One of the major challenges in designing highperformance VLSI circuits is diagnosis and analysis of speedpaths. A speedpath is a frequency-limiting critical path which affects the performance of a chip [2]. A speedpath that violates timing constraints at the post-silicon stage is called failing speedpath [3]. Speedpaths fail due to, e.g., timing variations induced by process, design, and environmental effects [2].Post-silicon validation involves applying test vectors to the chip in order to verify its correct behavior. When a speed failure is detected due to frequency constraints [4], the debug team identifies failing speedpaths. But this is a time-consuming process which requires a significant effort. Thus, automated debugging approaches to identify failing speedpaths are necessary to speed up the process.Recently, there is a range of works that considers timing analysis of circuits under variations. A survey of the works focusing on statistical static timing analysis (SSTA) is given in [5]. SSTA methods analyze a circuit considering timing variations. The work in [3] proposes a formal procedure based on an integer linear programming (ILP) formulation to diagnose segments of failing speedpaths due to process variations. ILP is a specific case of a system of linear constraints in which the variables can only take integer values. The ILP-based debug approach identifies segments of failing speedpaths that have a post-silicon delay larger than their estimated delay at the pre-silicon stage. Parameterized static timing analysis (PSTA) is used in [6] to obtain a variational model for every candidate speedpath from a given set of potential candidates. These variational models are then combined to create a cost function. This PSTA-based cost function determines the likelihood of any given combination of paths to be the selection of ''true'' speedpaths. The cost function is utilized by a branch-and-bound approach to Editor's notes: This paper presents a novel approach to automate speedpath debugging taking into account variations. The proposed technique is based on Boolean Satisfiability. The approach is based on converting the timing behavior of a circuit into the functional domain, inserting a variation logic into the model, and using a Boolean Satisfiability solver to extract failing speedpaths.determine the most probable failing speedpaths. In contrast to our approach, the previous approach needs a set of user-supplied ...

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confidence: 99%

Debug Automation for Logic Circuits Under Timing Variations

Dehbashi

Fey

2013

IEEE Des. Test

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“…The post-silicon timing validation is started by applying the test vectors to the chip while clock shrinking is performed [16] [17]. If an error is observed on the outputs or registers, the error is returned as an Erroneous Trace (ET).…”

Section: B Speedpath Debuggingmentioning

confidence: 99%

SAT-based speedpath debugging using X traces

Dehbashi

Fey

2014

2014 9th International Design and Test Symposium (IDT)

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Due to timing variations induced by process variations and environmental effects, speedpath debugging becomes a major concern in the design of high performance VLSI circuits. In this paper, we propose an efficient approach to speedpath debugging based on Boolean Satisfiability (SAT). We use a timediscrete model of the circuit for analyzing effects of delays within the circuit. For efficiency we overapproximate sensitized paths using advanced techniques from formal hardware verification. Our approach achieves 88% decrease in the size of the debug instance leading to 71% decrease in the debugging time compared to previous work. At the same time, our new approach achieves a high diagnosis accuracy.

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“…Typically, the last stage of the debug is to perform focus Ion beam (FIB) on-chip editing to confirm the fix of the bug. The authors in [11] describe methodology to debug speed-limiting paths using a CAD environment. In general, silicon debug is considered as an expensive approach and not applied in volume diagnosis.…”

Section: Background and Related Workmentioning

confidence: 99%

Statistical diagnosis of unmodeled systematic timing effects

Bastani

Callegari

Wang

et al. 2008

Proceedings of the 45th Annual Design Automation Conference

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Explaining the mismatch between predicted timing behavior from modeling and simulation, and the observed timing behavior measured on silicon chips can be very challenging. Given a list of potential sources, the mismatch can be the aggregate result caused by some of them both individually and collectively, resulting in a very large search space. Furthermore, observed data are always corrupted by some unknown statistical random noises. To overcome both challenges, this paper proposes a statistical diagnosis framework that formulates the diagnosis problem as a regression learning problem. In this diagnosis framework, the objective is to rank a set of features corresponding to the list of potential sources of concern. The rank is based on measured silicon path delay data such that a feature inducing a larger unexpected timing deviation is ranked higher. Experimental results are presented to explain the learning method. Diagnosis effectiveness will be demonstrated through benchmark experiments and on an industrial design.

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Silicon speedpath measurement and feedback into EDA flows

Cited by 31 publications

References 8 publications

Debug Automation for Logic Circuits Under Timing Variations

Debug Automation for Logic Circuits Under Timing Variations

SAT-based speedpath debugging using X traces

Statistical diagnosis of unmodeled systematic timing effects

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