Silicon photonics for compact, energy-efficient interconnects [Invited]

Abstract

͑Doc. ID 74779͒ The goal of the research program that we describe is to break the emerging performance wall in microprocessor development arising from limited bandwidth and density of on-chip interconnects and chip-to-chip (processor-tomemory) electrical interfaces. Complementary metal-oxide semiconductor compatible photonic devices provide an infrastructure for deployment of a range of integrated photonic networks, which will replace state-of-the-art electrical interconnects, providing significant gains at the system level. Scaling of wavelength-division-multiplexing (WDM) architectures using high-indexcontrast (HIC) waveguides offers one path to realizing the energy efficiency and density requirements of high data rate links. HIC microring-resonator filters are well suited to support add-drop nodes in dense WDM photonic networks with high aggregate data rates because they support high Q's and, due to their traveling-wave character, naturally support physically separated input and drop ports. A novel reconfigurable, "hitless" switch is presented that does not perturb the express channels either before, during, or after reconfiguration. In addition, multigigahertz operation of low-power, Mach-Zehnder silicon modulators as well as germanium-on-silicon photodiodes are presented.

Recent breakthroughs in carrier depletion based silicon optical modulators

“…On the other hand some state that in order for silicon photonics based interconnects to be attractive, the power consumed should not be larger than electrical interconnects which they are proposed to replace (~1 pj/bit) [53]. Some extend this argument stating that the energy should not exceed 100 fj/bit to surpass the efficiency of the 45 nm process node equalized on-chip electrical link [54]. The optical modulator is not the only element in the system and therefore can only consume a proportion of this target power.…”

All-Optical Comb Switch for Multiwavelength Message Routing in Silicon Photonic Networks

“…Likewise, the removal of carriers directs the signal back to the drop port. Carriers may be injected using an optical pump [7], [9], [10] or an electrical signal applied to a p-i-n junction across the waveguide [4]- [6].…”

“…The silicon-on-insulator materials system is attractive for realizing these photonic integrated circuit-based interconnection networks due to high index contrast and complementary metal-oxide-semiconductor process compatibility [2]- [10]. Furthermore blocks, having exhibited complex passive filters [2]- [4], as well as electrooptic and all-optical modulators [5]- [7]. Amidst this progress in silicon photonic technologies, a low-power high-speed compact switch capable of operating with high performance over a broad spectral bandwidth presents a key building block for routing multiwavelength data in integrated optical networks [7]- [10].…”

A Software Framework for Rapid Application-Specific Hybrid Photonic Network-on-Chip Synthesis

“…Table 2 shows delay values for 32 nm technology that we assumed, obtained from [48] and from device fabrication results [49]. The delay of an optimally repeated and sized copper wire at 32 nm was assumed to be 42 ps/mm [50].…”