Silicon Photonic Switches Hybrid-Integrated With CMOS Drivers

Rylyakov, Alexander V.; Schow, Clint L.; Lee, B. G.; Green, W. M. J.; Assefa, Solomon; Doany, F. E.; Yang, Min; Campenhout, Joris Van; Jahnes, C.; Kash, J. A.; Vlasov, Yurii A.

doi:10.1109/jssc.2011.2170638

Cited by 41 publications

(16 citation statements)

References 13 publications

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“…However, thermo-compression is also not an ideal solution, because it suffers from poorer chip-to-chip alignment tolerances than solder-reflow, and is a more complicated process to implement. Several solutions for flux-free solder-reflow bonding have been proposed, including (i) laser induced flipchip bonding using an In and Ag nano-particle based ink [14], (ii) Au-Sn solder which is relatively free from oxidation [9], (iii) wafer-level bonding in a vacuum chamber [15], and (iv) solderreflow in a forming-gas (i.e., H 2 buffered in N 2 ) to help decompose the oxides [16]. These novel approaches have not been widely implemented, because they are difficult to merge with established industrial flip-chip bonding production-lines, and require relatively costly modifications to the manufacturing infrastructure.…”

Section: Electronic-photonic Integrationmentioning

confidence: 99%

Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Lee¹,

Carroll²,

Scarcella³

et al. 2016

IEEE J. Select. Topics Quantum Electron.

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Integrated photonics is a promising route toward high-performance next-generation ICT and sensing devices. Although fiber-packaging is perhaps the most widely discussed obstacle to low-cost photonic devices, electronic-photonic integration and thermal-stabilization are also significant design considerations that need to be properly managed. Using a state-of-the-art Si-photonic optical-network-unit as a worked example, we illustrate some key challenges and solutions in the field of photonicpackaging. Specifically, we describe a novel solder-reflow bonding process for the face-to-face three-dimensional (3-D) integration of photonic and electronic integrated circuits, discuss current and future multichannel fiber-alignment techniques, and investigate the coefficient-of-performance of the thermo-electric cooler that stabilizes the temperature of the photonic components. The challenge of photonic-packaging is to simultaneously satisfy these electrical, optical, and thermal design requirements on small-footprint devices, while establishing a route to scalable commercial implementation.

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Section: Electronic-photonic Integrationmentioning

confidence: 99%

Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Lee¹,

Carroll²,

Scarcella³

et al. 2016

IEEE J. Select. Topics Quantum Electron.

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“…In the past few years, several silicon photonic switches have been reported [13][14][15][16][17][18]. They have a nearly 50-fold higher integration density than silica-based planar lightwave circuits [19].…”

Section: Introductionmentioning

confidence: 99%

Large-scale broadband digital silicon photonic switches with vertical adiabatic couplers

Seok¹,

Quack²,

Han³

et al. 2016

Optica

263

158

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Large-scale photonic switches are essential devices for energy-and cost-efficient optical communication networks in cloud and data-intensive computing. Silicon photonics is an attractive platform for high-density photonic integrated circuits with low manufacturing costs through the leveraging of existing advanced complementary metal-oxidesemiconductor processes. Many optical components such as lasers, modulators, splitters, and photodetectors have been successfully integrated on silicon; however, the quest for large-scale silicon photonic switches has remained elusive. Previous silicon photonic switches made of cascaded 1 × 2 or 2 × 2 building blocks have a limited port count (≤8 × 8) or excessive optical losses (>15 dB). Here, we present a 64 × 64 digital silicon photonic switch with a low on-chip insertion loss (3.7 dB) and broadband operation (300 nm). The measured switching time is 0.91 μs, and the extinction ratio is larger than 60 dB. The matrix switch with 4096 microelectromechanical-systems-actuated vertical adiabatic couplers has been integrated on a 8.6 mm × 8.6 mm chip. To our knowledge this is the largest monolithic switch, and the largest silicon photonic integrated circuit, reported to date. The passive matrix architecture of our switch is fundamentally more scalable than that of multistage switches.

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“…Hardware-software integrated silicon photonic subsystems controlled by means of custom firmware implemented in field programmable gate arrays (FPGAs) [14][15][16] and applicationspecific integrated circuits (ASICs) 17 have been demonstrated, offering the possibility for more advanced network functionalities.…”

Section: Introductionmentioning

confidence: 99%

Modular architecture for fully non-blocking silicon photonic switch fabric

Nikolova¹,

Calhoun²,

Liu³

et al. 2017

Microsyst Nanoeng

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Integrated photonics offers the possibility of compact, low energy, bandwidth-dense interconnects for large port count spatial optical switches, facilitating flexible and energy efficient data movement in future data communications systems. To achieve widespread adoption, intimate integration with electronics has to be possible, requiring switch design using standard microelectronic foundry processes and available devices. We report on the feasibility of a switch fabric comprised of ubiquitous silicon photonic building blocks, opening the possibility to combine technologies, and materials towards a new path for switch fabric design. Rather than focus on integrating all devices on a single silicon chip die to achieve large port count optical switching, this work shifts the focus towards innovative packaging and integration schemes. In this work, we demonstrate 1 × 8 and 8 × 1 microring-based silicon photonic switch building blocks with software control, providing the feasibility of a full 8 × 8 architecture composed of silicon photonic building blocks. The proposed switch is fully non-blocking, has path-independent insertion loss, low crosstalk, and is straightforward to control. We further analyze this architecture and compare it with other common switching architectures for varying underlying technologies and radices, showing that the proposed architecture favorably scales to very large port counts when considering both crosstalk and architectural footprint. Separating a switch fabric into functional building blocks via multiple photonic integrated circuits offers the advantage of piece-wise manufacturing, packaging, and assembly, potentially reducing the number of optical I/O and electrical contacts on a single die.

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Silicon Photonic Switches Hybrid-Integrated With CMOS Drivers

Cited by 41 publications

References 13 publications

Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Large-scale broadband digital silicon photonic switches with vertical adiabatic couplers

Modular architecture for fully non-blocking silicon photonic switch fabric

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