Silicon optical microbench technology with integrated micromachined interconnects

Banerjee, Srutarshi; Drayton, R.F.

doi:10.1109/ectc.2003.1216309

Cited by 3 publications

(1 citation statement)

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“…Each of these steps comes with its own attendant challenges related to the geometry of the via, the materials and/or processes used to insulate and metallize the vias, and the order in which these steps are performed. Myriad process flows are possible, and a variety of schemes have been proposed and developed to fabricate these connections [25][26][27].…”

Section: Integration Of Silicon Through-vias and Fine-pitch Wiringmentioning

confidence: 99%

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

et al. 2005

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System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and highperformance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two-and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. Highdensity wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a ''virtual chip'' using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electrooptic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

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Section: Integration Of Silicon Through-vias and Fine-pitch Wiringmentioning

confidence: 99%