Silicon on thin BOX: a new paradigm of the CMOSFET for low-power and high-performance application featuring wide-range back-bias control

Tsuchiya, R.; Horiuchi, M.; Kimura, S.; Yamaoka, Masanao; Kawahara, Takayuki; Maegawa, Satoru; Ippóshi, T.; Ohji, Yuzuru; Matsuoka, Hiroaki

doi:10.1109/iedm.2004.1419245

Cited by 130 publications

(70 citation statements)

References 7 publications

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“…SOTB transistors allow a wide back-bias control range for low-power and high-performance applications, because a thinner buried oxide under the lightly-doped and fully-depleted body region is formed as an SOI structure. As a result, by applying this to the SRAM cells, the static noise margins (SNMs) are improved by adding back feedback from the back gate to the front gate [10]. Moreover, SOTB has the smallest threshold voltage variability among bulk MOS, due to its low-dose channel [12].…”

Section: Silicon On Thin Buried Oxide (Sotb) Transistormentioning

confidence: 99%

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SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

Hioki

Kobayashi

et al. 2014

JLPEA

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Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB OPEN ACCESSJ. Low Power Electron. Appl. 2014, 4 189(silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed.Keywords: field programmable gate array (FPGA); static leakage power reduction; fine-grained body biasing; silicon on thin buried oxide (SOTB)

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Section: Silicon On Thin Buried Oxide (Sotb) Transistormentioning

confidence: 99%

“…The SOTB (silicon on thin buried oxide) transistor [10] has an excellent Vt controllability. Compared with the bulk MOS transistor, a wider variation range of the threshold voltage is promised in principle, because it is formed using a thinner buried oxide under a lightly-doped and fully-depleted body region.…”

Section: Introductionmentioning

confidence: 99%

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

Hioki

Kobayashi

et al. 2014

JLPEA

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“…The static noise margins (SNM) of 0.357 V at V dd = 1.2 V and 0.142 V at V dd = 0.6 V indicate a much more stable operation in comparison with conventional bulk ones. The fail bit count (FBC) analysis indicated that the SOTB-SRAM can operate as low as 0.6 V, whereas the bulk SRAM with the same cell size operates at 1.1 V (Tsuchiya et al, 2009). The variability of SOTB CMOSFETs has a significant impact on standby power consumption.…”

Section: Reduction Of Power Consumptionmentioning

confidence: 99%

“…To solve the V th variation problem due to RDF and satisfy the demand from circuit designers, we have proposed the SOTB CMOSFET (Tsuchiya et al, 2004;Ishigaki et al, 2008;Morita et al, 2008). Figure 1 shows a schematic cross-section of the SOTB structure.…”

Section: Features Of Sotb Cmosfetmentioning

confidence: 99%

Ultralow-power LSI Technology with Silicon on Thin Buried Oxide (SOTB) CMOSFET

Ishigaki¹,

Tsuchiya²,

Morita³

et al. 2010

Solid State Circuits Technologies

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“…It consists of a host microprocessor GeyserCUBE-SOTB and several accelerators which provide the same TCI interface. All chips use novel silicon on insulator (SOI) technology called silicon-onthin-buried oxide [12][13] that can work with low supply voltage. To cope with problems on the uni-directional ring network, a bi-directional escalator network is proposed for CUBE-SOTB.…”

Section: Introductionmentioning

confidence: 99%

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

Nomura

Matsushita

Kadomoto

et al. 2018

IJNC

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A wireless inductive coupling ThruChip Interface (TCI) is a flexible system-in-package (SiP) technique which enables to build a powerful interconnection network between stacked chips. For easy use of TCI, we have developed intellectual properties (IPs), and proposed an interconnection network which can make the use of IPs. We also developed a real chip embedded the IP, and evaluated the performance. By stacking multiple chips with the proposed IP, an inter-chip network with link-to-link flow control by piggyback control is established. The new proposed escalator network which uses piggyback of the credit packets outperforms the ring network used in the first prototype by 28%-59% in terms of throughput. The performance overhead by the piggyback control was less than 3%-4% of that without control messages.

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Silicon on thin BOX: a new paradigm of the CMOSFET for low-power and high-performance application featuring wide-range back-bias control

Cited by 130 publications

References 7 publications

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

Ultralow-power LSI Technology with Silicon on Thin Buried Oxide (SOTB) CMOSFET

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

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