A process is described for the realization of via holes for microstrip transmission lines and passive elements on high resistivity Silicon (p > 4000 Rcm, 100 mm diameter, 100 pm thickness). Via hole etching with vertical sidewalls is performed using an advanced silicon etch (ASE) process. The measured and simulated inductance of the gold metallized via hole is 22 pH. Measurements on a ring resonator -isolated by 550 nm thermal oxide from the substrate -yield a dielectric constant E, = 11.2 and a loss tangent tan6 around for the 4000 Rcm silicon substrate. Attenuation of microstrip trans-mission lines are -= 0.1 dB/mm at 20 GHz.