Silicon Hot Spot Remediation With a Germanium Self Cooling Layer

Abstract

Driven by shrinking feature sizes, microprocessor hot spots have emerged as the primary driver for on-chip cooling of today’s IC technologies. Current thermal management technologies offer few choices for such on-chip hot spot remediation. A solid state germanium self-cooling layer, fabricated on top of the silicon chip, is proposed and demonstrated to have great promise for reducing the severity of on-chip hot spots. 3D thermo-electrical coupled simulations are used to investigate the effectiveness of a bi-layer device containing a germanium self-cooling layer above an electrically insulated silicon layer. The parametric variables of applied current, cooler size, silicon percentage, and total die thickness are sequentially optimized for the lowest hot spot temperature compared to a non-self-cooled silicon chip. Results suggest that the localized self-cooling of the germanium layer coupled with the higher thermal conductivity of the silicon chip can significantly reduce the temperature rise resulting from a micro-scaled hot spot.

A Hybrid Multi-gate Model of a Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) Device Incorporating GaN-substrate Thermal Boundary Resistance

“…Summarizing the above simplifications, the spreading width equation assumes linear dependence on GaN thickness and quadratic dependence on TBR. This facilitates the use of the surface fitting procedure by Nochetto (38) to provide the 2-D spreading width shown in equation 6, where g represents the GaN thickness in µm and TBR represents the thermal boundary resistance in m 2 K/GW. For the parameter space given in table 2, the surface fit is shown graphically in figure 16 along with the corresponding error between the surface fit and the FEA derived values.…”