Silicon Damage Caused by Hydrogen Containing Plasmas

Frieser, R. G.; Montillo, F. J.; Zingerman, N. B.; Chu, W. K.; Mäder, Sebastian

doi:10.1149/1.2119559

Cited by 71 publications

(18 citation statements)

References 3 publications

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“…236)], C 2 F 6 (Freon 116), and C 3 F 8 (Freon 218) were used in the early days to etch SiO 2 , 28,29 usually with addition of O 2 when selectivities to resist and/or silicon were not critical, and polymer control was important. Hydrogen addition to the above fluorocarbons was used to increase selectivity to silicon, 28,29,237 with the drawbacks of polymer formation, decreased etch rate, 237,238 and deep penetration of hydrogen into the silicon substrate [239][240][241][242][243][244][245][246][247] that can lead to device degradation if not annealed properly. In applications where this is not an issue (such as patterning of waveguides), hydrogen may be used as an additive to control selectivity to silicon and/or photoresists.…”

Section: Dielectricsmentioning

confidence: 99%

Plasma etching: Yesterday, today, and tomorrow

Donnelly¹,

Kornblit²

2013

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

648

422

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The field of plasma etching is reviewed. Plasma etching, a revolutionary extension of the technique of physical sputtering, was introduced to integrated circuit manufacturing as early as the mid 1960s and more widely in the early 1970s, in an effort to reduce liquid waste disposal in manufacturing and achieve selectivities that were difficult to obtain with wet chemistry. Quickly,the ability to anisotropically etch silicon, aluminum, and silicon dioxide in plasmas became the breakthrough that allowed the features in integrated circuits to continue to shrink over the next 40 years. Some of this early history is reviewed, and a discussion of the evolution in plasma reactor design is included. Some basic principles related to plasma etching such as evaporation rates and Langmuir–Hinshelwood adsorption are introduced. Etching mechanisms of selected materials, silicon,silicon dioxide, and low dielectric-constant materials are discussed in detail. A detailed treatment is presented of applications in current silicon integrated circuit fabrication. Finally, some predictions are offered for future needs and advances in plasma etching for silicon and nonsilicon-based devices.

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Section: Dielectricsmentioning

confidence: 99%

Plasma etching: Yesterday, today, and tomorrow

Donnelly¹,

Kornblit²

2013

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

648

422

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“…170,171) Furthermore, some metal-induced damage to the silicon crystal structure is observed at the thin modified layer near the bottom surface. 143,[174][175][176][177][178][179] The thickness of the modified layer approximately ranges between 5 and 50 nm; this thickness prevents the formation of a silicide layer, causes an anomalous increase in the contact resistance, and degrades the device performance. The damage-induced thin modified layer formed at the bottom of the HARC is removed by applying additional CDE/cleaning using CF 4 , NF 3 , or SF 6 plasmas.…”

Section: Typical Damage During Harc Etching and Removal Of Damaged Layermentioning

confidence: 99%

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

Abe¹,

Yoneda

Fujiwara

2008

jjap

279

163

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Plasma etching technologies such as reactive ion etching (RIE), isotropic etching, and ashing/plasma cleaning are the currently used booster technologies for manufacturing all silicon devices based on the scaling law. The needs-driven conversion from the wet etching process to the plasma/dry etching process is reviewed. The progress made in plasma etching technologies is described from the viewpoint of requirements for the manufacturing of devices. The critical applications of RIE, isotropic etching, and plasma ashing/cleaning to form precisely controlled profiles of high-aspect-ratio contacts (HARC), gate stacks, and shallow trench isolation (STI) in the front end of line (FEOL), and also to form precise via holes and trenches used in reliable Cu/low-k (low-dielectric-constant material) interconnects in the back end of line (BEOL) are described in detail. Some critical issues inherent to RIE processing, such as the RIE-lag effect, the notch phenomenon, and plasma-induced damage including charge-up damage are described. The basic reaction mechanisms of RIE and isotropic etching are discussed. Also, a procedure for designing the etching process, which is strongly dependent on the plasma reactor configuration, is proposed. For the more precise critical dimension (CD) control of the gate pattern for leading-edge devices, the advanced process control (APC) system is shown to be effective.

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“…Due to the small mass and radius of a hydrogen atom compared with those of a silicon atom, damage formation of Si surfaces by energetic incident H þ ions 8,9,13 is known to be different from that by heavier incident ions such Ar þ . Earlier studies [14][15][16][17] on RIE processes by hydrogen containing plasmas recognized Si damage formed by H þ ion bombardment as a cause of lifetime degradation of metal-oxide-semiconductor capacitors. What has not been discussed so much is a possibility of Si damage formation by energetic ions at oblique angle impact.…”

Section: Introductionmentioning

confidence: 99%

Molecular dynamic simulation of damage formation at Si vertical walls by grazing incidence of energetic ions in gate etching processes

Mizotani

Isobe

Hamaguchi

2015

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

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During gate etching processes of multigate fin-type field effect transistors (finFETs), energetic ions may hit the vertical walls at grazing angles and form damaged layers there. Such damages, if formed, can affect the device performance since part of the Si vertical walls of a finFET structure is used as a conductive channel. In this article, possible damage formation mechanisms at a Si vertical wall by energetic incidence of hydrogen ions (H þ ) and other heavier ions are discussed based on molecular dynamics simulation. In typical plasma processing conditions, incident ions are highly directional toward the wafer surface and therefore ions that hit such a vertical wall do so only at nearly grazing angles. It has been found in this study that the penetration depth of H þ into a Si substrate is weakly dependent on the incident angle and therefore ions at grazing incidence can form deep damage. The results indicate that, in gate etching processes with HBr plasmas or other plasmas with hydrogen, control of energetic hydrogen ion bombardment is critical in minimizing possible surface damage at Si vertical walls. V

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Silicon Damage Caused by Hydrogen Containing Plasmas

Cited by 71 publications

References 3 publications

Plasma etching: Yesterday, today, and tomorrow

Plasma etching: Yesterday, today, and tomorrow

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

Molecular dynamic simulation of damage formation at Si vertical walls by grazing incidence of energetic ions in gate etching processes

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