Silicon-based tunneling field-effect transistor with elevated germanium source formed on (110) silicon substrate

Abstract

Physical-gap-channel graphene field effect transistor with high on/off current ratio for digital logic applications Appl. Phys. Lett. 101, 143102 (2012) Short channel mobility analysis of SiGe nanowire p-type field effect transistors: Origins of the strain induced performance improvement Appl. Phys. Lett. 101, 143502 (2012) Terahetz detection by heterostructed InAs/InSb nanowire based field effect transistors Development of high-performance fully depleted silicon-on-insulator based extended-gate field-effect transistor using the parasitic bipolar junction transistor effect Appl. Phys. Lett. 101, 133703 (2012) Abnormal interface state generation under positive bias stress in TiN/HfO2 p-channel metal-oxide-semiconductor field effect transistors

Modelling doping design in nanowire tunnel-FETs based on group-IV semiconductors

“…Nonetheless it is relatively difficult to integrate III-V semiconductors on a Si platform. Various TFET research works have been done using Ge [9][10][11], and SiGe [12][13][14][15].…”

Lateral energy band profile modulation in tunnel field effect transistors based on gate structure engineering

“…In many studies on TFETs, including examinations of hetero-source, 11,12 dual-material-gate, 27 and hetero-gate-dielectric 28 structures, the BPM effect was actually used to improve the properties of the devices, but it was not explained clearly how this was achieved. In our study, the BPM effect was achieved directly by introducing different gate configurations with lateral work function differences.…”

“…[8][9][10] However, some issues remain unresolved in TFET research. Previous investigations have focused on the development of special structures to boost the on-state current (I on ) of TFETs, such as source-channel hetero-junctions, 11,12 ultra-thin body SOIs, 13 and heavily doped tunnel junctions. 14 However, these special structures require the use of certain key techniques, and these techniques are difficult to achieve using a standard CMOS fabrication process flow.…”

A review of thin-film transistors/circuits fabrication with 3D self-aligned imprint lithography

“…The FET uses either holes (p-channel) or electrons (n-channel) for conduction between source and drain electrodes. A gate electrode, which is separated from the semiconductor by a dielectrics layer, is used to control the source-drain current through varying the applied gate voltage [38]. The most commonly used FET design is the metal-oxide-semiconductor field effect transistor (MOSFET), where heavily doped regions are used to form source/drain electrodes [39].…”