Silicon and Group IV Photonics

Radamson, Henry H.; Thylén, Lars

doi:10.1016/b978-0-12-419975-0.00003-9

Cited by 12 publications

(15 citation statements)

References 58 publications

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“…The SiGe peak is aligned with Si along K// indicating minor strain relaxation. The mismatch parameters were obtained from this HRRLM and a parabolic relation was used to determine the lattice constant of SiGe layer and the Ge content [2,[11][12]. These calculations showed highly strained Si 0.60 Ge 0.40 layers in FinFETs.…”

Section: Resultsmentioning

confidence: 99%

“…FinFET. The new design improves the transistor performance by exerting an electrostatic control to the transistor channel and decreases the short-channel effects [1][2][3][4][5][6][7]. For such structures, SiGe layers were grown selectively on source/drain regions as stressor material to create uniaxial strain in the channel region and to enhance the carrier mobility [1][2][3][4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

“…In FinFETs, the shape, dimensions (height and width) and doping level of the original Si fin have importance in carrier transport [2,[8][9]. The shape of fin plays the role how stress from SiGe is exerted from sidewalls to the central part of body.…”

Section: Introductionmentioning

confidence: 99%

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Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

Radamson

Luo

Qin

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 10 20 cm −3 . The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO 2 as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

Radamson

Luo

Qin

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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“…Beyond those inventions, the shape of CMOS has already been changed from planar to 3D by overcoming a lot of integration issues [ 4 ]. By entering the 10 nm technology node, pure silicon-based channel is being gradually replaced with silicon-germanium (SiGe) or germanium (Ge), and III-V materials, because they have better mobility of- 40,000 cm 2 V −1 s −1 for InGaAs (for electrons) and 1900 cm 2 V −1 s −1 for Ge (for holes) compared to 1400 cm 2 V −1 s −1 for electrons and 450 cm 2 V −1 s −1 for holes of silicon [ 5 , 6 ]. Not only are the channel materials changing, but so is device shape, from simple fin-like to fully depleted on insulator or nanowire ones [ 7 ].…”

Section: Introductionmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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“…In recent years, with the continuous scaling-down of CMOS technology nodes, high-mobility channel materials (SiGe, Ge and III–V material such as InGaAs) and novel device designs (horizontally/vertically Gate-All-Around (GAA) stacked nanowires) have been under investigation [ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 ]. The high mobility of n-GaN and the current possibility of achieving an enhancement mode in non-polar GaN have also been extensively researched with gallium nitride Fin Field-Effect Transistors (FinFETs) [ 14 , 15 ].…”

Section: Introductionmentioning

confidence: 99%

Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/High-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium

et al. 2020

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With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have emerged as excellent choices. The driving forces for this choice are the full control of the short channel effect and the high carrier mobility in the channel region. In this work, a novel process to form the structure for a VGAA transistor with a Ge channel is presented. The structure consists of multilayers of Si0.2Ge0.8/Ge grown on a Ge buffer layer grown by the reduced pressure chemical vapor deposition technique. The Ge buffer layer growth consists of low-temperature growth at 400 °C and high-temperature growth at 650 °C. The impact of the epitaxial quality of the Ge buffer on the defect density in the Si0.2Ge0.8/Ge stack has been studied. In this part, different thicknesses (0.6, 1.2 and 2.0 µm) of the Ge buffer on the quality of the Si0.2Ge0.8/Ge stack structure have been investigated. The thicker Ge buffer layer can improve surface roughness. A high-quality and atomically smooth surface with RMS 0.73 nm of the Si0.2Ge0.8/Ge stack structure can be successfully realized on the 1.2 µm Ge buffer layer. After the epitaxy step, the multilayer is vertically dry-etched to form a fin where the Ge channel is selectively released to SiGe by using wet-etching in HNO3 and H2O2 solution at room temperature. It has been found that the solution concentration has a great effect on the etch rate. The relative etching depth of Ge is linearly dependent on the etching time in H2O2 solution. The results of this study emphasize the selective etching of germanium and provide the experimental basis for the release of germanium channels in the future.

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Silicon and Group IV Photonics

Cited by 12 publications

References 58 publications

Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

State of the Art and Future Perspectives in Advanced CMOS Technology

Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/High-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium

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