Signature Rollback - A Technique for Testing Robust Circuits

Abstract

Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a robust design has become mandatory. However, standard structural test procedures still address classical fault models and cannot deal with the non-deterministic behavior caused by parameter variations and other reasons. Chips may be rejected, even if the test reveals only non-critical failures that could be compensated during system operation. This paper introduces a scheme for embedded test, which can distinguish critical permanent and noncritical transient failures for circuits with time redundancy. To minimize both yield loss and the overall test time, the scheme relies on partitioning the test into shorter sessions. If a faulty signature is observed at the end of a session, a rollback is triggered, and this particular session is repeated. An analytical model for the expected overall test time provides guidelines to determine the optimal parameters of the scheme.

Diagnostic Test of Robust Circuits

“…In case of a mismatch, the test is repeated immediately to distinguish transient from permanent faults. As shown in [8], for growing values of N the yield improvement increases and the test time decreases. But as N increases, the hardware overhead also increases due to the storage required for the reference data.…”

“…But as N increases, the hardware overhead also increases due to the storage required for the reference data. The analytical model developed in [8] provides guidelines to adjust the parameters of the scheme, such that for a given failure rate the best trade-off between hardware overhead, yield improvement and test time is obtained.…”

“…In [8] a BIST scheme based on the STUMPS architecture has been proposed for circuits with time redundancy [9]. This scheme can distinguish between transient and permanent faults and reduces the yield loss this way.…”

“…In both cases a more precise diagnosis is important to improve the production process: an accumulation of transient faults may indicate a particularly susceptible structure in the circuit, while the presence of many permanent faults may indicate a problem in the manufacturing process. This paper combines the signature rollback scheme developed in [8] and [10] with a procedure for direct diagnosis. This diagnostic technique is not confined to the stuck-at fault model and supports the diagnosis of a large variety of defect mechanisms [11].…”

A fault tolerant response analyzer with self-error-correction capability

“…Even in a BIST scheme, this issue also arises both in the production test and the field test (testing LSIs after shipped). For example, it was reported that transient faults occur while a circuit-under-test (CUT) is tested with BIST circuits, and they change the result of the testing [2]. In other words, it can consider that the occurrence of faults in the BIST circuits during testing a CUT in the field may cause not only lower availability of LSIs but also significant system failures in particular.…”