A fault tolerant response analyzer with self-error-correction capability

Abstract

Reliable built-in self-test (Reliable BIST) scheme equips to be tolerant of faults, which occur in embedded BIST circuits. To realize reliable BIST, it is required to recover itself from transient errors of its embedded BIST circuits. In this paper, we propose a self-error-correctable response analyzer (RA) for a reliable BIST scheme. Experimental results show that test-reliability of SECRA is superior to TMR MISRs on the assumption that transient faults occur in RA during testing CUTs.

Novel modified memory built in self‐repair (MMBISR) for SRAM using hybrid redundancy‐analysis technique

“…Several other galloping bit/patterns-based algorithms were also developed to enhance the fault coverage of targeted fault classes [11,12]. The modified galloping pattern-based and checkerboard algorithms also provide good diagnosis speed and fault coverage [13][14][15][16][17][18]. In these designs, the MBISR hardware consists of three main modules i.e.…”

“…March C-testing algorithm is used as a base algorithm for MBIST. The modified MARCH algorithm CHECKERMARC [21] can also be used to design MBIST module but to compare the results with [17,[22][23][24][25], a simple MARCH Calgorithm is considered as a first choice. This MARCH C-based MBIST module embedded in the SRAM memory and can work concurrently with other two modules.…”