Novel modified memory built in self‐repair (MMBISR) for SRAM using hybrid redundancy‐analysis technique

Abstract

The article presents a new augmented and improved MMBISR for SRAM using hybrid redundancy analysis (HRA). The presented algorithm is the augmented version of essential spare pivoting (ESP) and local repair most (LRM). The algorithm proposes the best solution by providing optimised set of row and column combination which were suitable for the repairing process. In the proposed redundancy analysis (RA) algorithm, the fault dictionary can be updated or fixed concurrently, according to MBIST needs and supplied control signals. The row and column pivots and repair requests are also serviced according to precedency list prepared by the comparing actions. The comparative analysis with LRM and ESP-RA algorithms shows that the proposed algorithm has reduced complexity and tracing time in terms of implementation and in terms of finding row and column pivots. For the implementation, a MBISR hardware structure is designed and tested using suitable VHDL descriptions that were targeted for Virtex-5, xc5vlx30 FPGA. The results were also justified that the proposed algorithm is quite effective as the repair rate is increased up to 4% compared to the ESP. However, some nominal area penalty is observed as compared to ESP.

Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM

“…In 2019, Pundir [25] presented improved modified memory Built-In Self-Repair (MM-BISR) for Static Random Access Memory utilizing hybrid redundancy analysis (HRA). The augmented version of ESP and LRM provides a better solution for an optimized set of rows and columns appropriate to the repair process.…”

“…Then, the proposed hybrid technique is the combined execution of both the Deep reinforcement learning (DQL) [24] and Bit-Swapping-based linear feedback shift register (BSLFSR) [25]; hence it is named the DQL-BSLFSR technique.…”