Signal processing for velocity selective recording systems using analogue delay lines

Rieger, Robert; Taylor, J.; Clarke, Chris

doi:10.1109/iscas.2012.6271725

Cited by 3 publications

(8 citation statements)

References 8 publications

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“…v3+ and v3 -are the velocities where the normalized amplitude of the tuning curve drops to either side of the matched velocity (v3+ above and v3 -below). More recently, an additional parameter, R v , has been introduced in an attempt to quantify velocity resolution [6]. R v is defined as Δv/v, where Δv is minimum available velocity step at propagation velocity v. It was suggested in [6] that a reasonable maximum value for R v across the velocity band of interest would be about 0.1.…”

Section: B Vsr Signal Processing Methods 1) Conventional Vsr Signal mentioning

confidence: 99%

“…More recently, an additional parameter, R v , has been introduced in an attempt to quantify velocity resolution [6]. R v is defined as Δv/v, where Δv is minimum available velocity step at propagation velocity v. It was suggested in [6] that a reasonable maximum value for R v across the velocity band of interest would be about 0.1. For example, with the values in the previous paragraph, at a propagation velocity of 10 m/s, R v = 0.11, which is satisfactory, but at 100 m/s, this has risen to 0.5, which is clearly not.…”

Section: B Vsr Signal Processing Methods 1) Conventional Vsr Signal mentioning

confidence: 99%

“…Its properties have subsequently been discussed [1]- [6]. Although it provides a very robust approach to the problem of velocity spectral analysis, there are a number of key weaknesses, as noted in section II.B.1 (Conventional VSR signal processing: 'delayand-add').…”

Section: A the Need For The New Methods Proposed In This Papermentioning

confidence: 99%

“…Block 2 is referred to as the electrode unit and is intended to be mounted on the MEC for optimum performance. It consists of a set of speciallydesigned low noise differential amplifiers (nominal gain 10,000) whose 10 bipolar (or single differential) outputs are digitized (10 bits resolution) and multiplexed into one channel for transmission along the implantable cable [6]. In a distributed sensor architecture, several electrode units are placed at different sites in the peripheral nervous system and connected by implanted cables to a single monitoring unit [7].…”

Section: A System Description 1) Conventional Vsr Signal Processing:mentioning

confidence: 99%

See 3 more Smart Citations

Improved Signal Processing Methods for Velocity Selective Neural Recording Using Multi-Electrode Cuffs

Al-Shueli

Clarke

Donaldson

et al. 2014

IEEE Trans. Biomed. Circuits Syst.

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Section: B Vsr Signal Processing Methods 1) Conventional Vsr Signal mentioning

confidence: 99%

Section: B Vsr Signal Processing Methods 1) Conventional Vsr Signal mentioning

confidence: 99%

Section: A the Need For The New Methods Proposed In This Papermentioning

confidence: 99%

Section: A System Description 1) Conventional Vsr Signal Processing:mentioning

confidence: 99%

See 2 more Smart Citations

Improved Signal Processing Methods for Velocity Selective Neural Recording Using Multi-Electrode Cuffs

Al-Shueli

Clarke

Donaldson

et al. 2014

IEEE Trans. Biomed. Circuits Syst.

Self Cite

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“…These processes are quite costly in terms of power consumption and die area. For example in a typical 10-channel VSR system realised in 0.35 µm CMOS technology, the 'basic' functions (MUX/DMUX etc) consume about 40 mW, adding the signal processing functions required for VSR adds a further 70 mW and more than doubles the die area [9] [10].…”

Section: A Switched-capacitor Front-end For Velocity-selective Eng Rementioning

confidence: 99%

A Switched-Capacitor Front-End for Velocity-Selective ENG Recording

Rieger

Taylor

2013

IEEE Trans. Biomed. Circuits Syst.

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Multi-electrode cuffs (MECs) have been proposed as a means for extracting additional information about the velocity and direction of nerve signals from multi-electrode recordings. This paper discusses certain aspects of the implementation of a system for velocity selective recording (VSR) where multiple neural signals are matched and summed to identify excited axon populations in terms of velocity. The approach outlined in the paper involves the replacement of the digital signal processing stages of a standard delay-matched VSR system with analogue switched-capacitor (SC) delay lines which promises significant savings in both size and power consumption. The system specifications are derived and two circuits, each composed of low-noise preamplifiers connecting to a 2nd rank SC gain stage, are evaluated. One of the systems provides a single-ended SC stage whereas the other system is fully differential. Both approaches are shown to provide the low-noise, low-power operation, practically identical channel gains and sample delay range required for VSR. Measured results obtained from chips fabricated in 0.8 μ m CMOS technology are reported.

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A Low Power Linear Phase Programmable Long Delay Circuit

Rodriguez‐Villegas

Logesparan

Casson

2014

IEEE Trans. Biomed. Circuits Syst.

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A novel linear phase programmable delay is being proposed and implemented in a 0.35 μm CMOS process. The delay line consists of N cascaded cells, each of which delays the input signal by Td/N, where Td is the total line delay. The delay generated by each cell is programmable by changing a clock frequency and is also fully independent of the frequency of the input signal. The total delay hence depends only on the chosen clock frequency and the total number of cascaded cells. The minimum clock frequency is limited by the maximum time a voltage signal can effectively be held by an individual cell. The maximum number of cascaded cells will be limited by the effects of accumulated offset due to transistor mismatch, which eventually will affect the operating mode of the individual transistors in a cell. This latter limitation has however been dealt with in the topology by having an offset compensation mechanism that makes possible having a large number of cascaded cells and hence a long resulting delay. The delay line has been designed for scalp-based neural activity analysis that is predominantly in the sub-100 Hz frequency range. For these signals, the delay generated by a 31-cell cascade has been demonstrated to be programmable from 30 ms to 3 s. Measurement results demonstrate a 31 stage, 50 Hz bandwidth, 0.3 s delay that operates from a 1.1 V supply with power consumption of 270 nW.

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Signal processing for velocity selective recording systems using analogue delay lines

Cited by 3 publications

References 8 publications

Improved Signal Processing Methods for Velocity Selective Neural Recording Using Multi-Electrode Cuffs

Improved Signal Processing Methods for Velocity Selective Neural Recording Using Multi-Electrode Cuffs

A Switched-Capacitor Front-End for Velocity-Selective ENG Recording

A Low Power Linear Phase Programmable Long Delay Circuit

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