A Low Power Linear Phase Programmable Long Delay Circuit

Abstract

A novel linear phase programmable delay is being proposed and implemented in a 0.35 μm CMOS process. The delay line consists of N cascaded cells, each of which delays the input signal by Td/N, where Td is the total line delay. The delay generated by each cell is programmable by changing a clock frequency and is also fully independent of the frequency of the input signal. The total delay hence depends only on the chosen clock frequency and the total number of cascaded cells. The minimum clock frequency is limited by the maximum time a voltage signal can effectively be held by an individual cell. The maximum number of cascaded cells will be limited by the effects of accumulated offset due to transistor mismatch, which eventually will affect the operating mode of the individual transistors in a cell. This latter limitation has however been dealt with in the topology by having an offset compensation mechanism that makes possible having a large number of cascaded cells and hence a long resulting delay. The delay line has been designed for scalp-based neural activity analysis that is predominantly in the sub-100 Hz frequency range. For these signals, the delay generated by a 31-cell cascade has been demonstrated to be programmable from 30 ms to 3 s. Measurement results demonstrate a 31 stage, 50 Hz bandwidth, 0.3 s delay that operates from a 1.1 V supply with power consumption of 270 nW.

A 950 nW Analog-Based Data Reduction Chip for Wearable EEG Systems in Epilepsy

“…The SC delay circuit of [30] has been modified to be suitable for adaptation in this work. A unity gain buffering stage is added between the C 5 filter and the SC delay circuit to isolate the filter output from the switching transients.…”

“…The compounded effect of offset voltages will result in signal distortion at the delay circuit output. Therefore, the authors of [30] recommend placing an offset correction cell incorporating floating gate transistors, as shown in Fig. 9b within the delay line.…”

“…Furthermore, a significant loss of gain (-10.33 dB) has been reported in [30], due to the parasitic capacitance at the floating gate nodes in the offset correction cells.…”

A Seizure-Based Power Reduction SoC for Wearable EEG in Epilepsy

“…The line length equation of (1) was implemented by subtracting the original signal from a delayed copy of itself, followed by a rectifier and integrator. The delay line was created by cascading six of the delay cells proposed in [22], each consisting of two SC stages and controlled by complementary clock signals. The delay cells were clocked at 128 Hz with a duty cycle of 50%, resulting in an overall delay of 47 ms for the six cascaded delay cells.…”