SiGe HBTs With Normal High-Speed Emitter-Up and Reverse Low-Power Collector-Up Operation

Choi, L.J.; Sibaja-Hernandez, A.; Venegas, Rafael; Huylenbroeck, Stefaan Van; Decoutere, Stefaan

doi:10.1109/ted.2007.910575

Cited by 15 publications

(1 citation statement)

References 17 publications

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“…Moreover, it was suggested that an inverted transistor design with a smaller collector on top and a larger emitter at bottom should have speed advantages over the conventional emitter-up (E-up) structure [4]. Practically, in the collector-up (C-up) structure, the base-collector capacitance and the collector resistance are very small, which can lead to good RF performance [5]. Hence, C-up HBTs are expected to comply with the specifications for compact and highly thermal-stable HPA designs.…”

Section: Introductionmentioning

confidence: 99%

Thermal analysis of multi‐finger GaInP collector‐up heterojunction bipolar transistors with miniature heat‐dissipation packaging structures

Lee¹,

Tseng²,

Chou³

2009

Int J Numerical Modelling

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SUMMARYWe build up a finite element modeling (FEM) approach to analyze the thermal performance of collector-up (C-up) heterojunction bipolar transistor (HBTs) with a heat-dissipation via configuration. Highly compact heat-dissipation packaging structures of GaInP/GaAs C-up HBTs have been designed and evaluated systematically. In this work, we devise the 2-D and 3-D models to simulate the actual devices and to investigate the temperature distribution behavior. Results from 2-D model indicate that the large heatdissipation via configuration can be further reduced by 29% to meet the requirement of HBT-based small high-power amplifiers (HPAs) for the cellular phones. Furthermore, the demonstrated results show that the maximum temperature within the collector calculated from 3-D model is lower than that from 2-D model. In the 3-D analysis, it is revealed that the configuration can be reduced by 32%. Therefore, thinning the heatdissipation via constructed underneath the GaInP/GaAs C-up HBT should be helpful for miniaturization of HBT-based HPAs in future mobile communication systems.

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Section: Introductionmentioning

confidence: 99%

Thermal analysis of multi‐finger GaInP collector‐up heterojunction bipolar transistors with miniature heat‐dissipation packaging structures

Lee¹,

Tseng²,

Chou³

2009

Int J Numerical Modelling

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Si1−xGex growth using Si3H8 by low temperature chemical vapor deposition

et al. 2010

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Low temperature epitaxial growth of group-IV alloys is a key process step to realize the advanced Si-based devices. In order to keep high growth rate below 600 °C, trisilane (Si3H8) was used for their growth as an alternative Si precursor gas. Then, we compared the use of Si3H8 versus SiH4 for Si1-xGex growth in H2 and N2 as carrier gas by low temperature chemical vapor deposition. By using Si3H8 and controlling GeH4 flow rate, Si1-xGex growth with high growth rate and wide range of Ge concentration has been achieved compared to SiH4-based process. The growth rate and Ge concentration in Si1-xGex with Si3H8 grown at 600 °C ranged from 11 to 74nm/min and from 0 to 40%, respectively. The obtained growth rates with Si3H8 are between 1.5 and 6 times higher than for SiH4 at a given growth condition. Si3H8-based in-situ B-and C-doped Si1-xGex growth with high growth rate was also demonstrated.

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Simulation and modeling of heat-dissipation packaging for nanoscale GaInP/GaAs collector-up HBTs

Chang

Tseng

2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

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SiGe HBTs With Normal High-Speed Emitter-Up and Reverse Low-Power Collector-Up Operation

Cited by 15 publications

References 17 publications

Thermal analysis of multi‐finger GaInP collector‐up heterojunction bipolar transistors with miniature heat‐dissipation packaging structures

Thermal analysis of multi‐finger GaInP collector‐up heterojunction bipolar transistors with miniature heat‐dissipation packaging structures

Si1−xGex growth using Si3H8 by low temperature chemical vapor deposition

Simulation and modeling of heat-dissipation packaging for nanoscale GaInP/GaAs collector-up HBTs

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