Si1−xGex growth using Si3H8 by low temperature chemical vapor deposition

Takeuchi, Shinichi; Nguyen, Ngoc Duy; Goosens, Jozefien; Caymax, Matty; Loo, Roger

doi:10.1016/j.tsf.2009.10.047

Cited by 14 publications

(3 citation statements)

References 15 publications

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“…1b͒. 13 This growth enhancement is caused by the faster H desorption from Ge sites due to the weaker Ge-H bond 14 in case there is no oversaturation with H from an H 2 environment. Based on these considerations, a deposition test was set up based on SiH 4 in N 2 carrier gas flow in the temperature range of 500-575°C.…”

Section: Si Passivation With a Sih 4 -Based Deposition Processmentioning

confidence: 99%

The Influence of the Epitaxial Growth Process Parameters on Layer Characteristics and Device Performance in Si-Passivated Ge pMOSFETs

Caymax

Leys

Mitard

et al. 2009

J. Electrochem. Soc.

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Recently, the best 65 nm Ge p-channel metal-oxide-semiconductor field-effect transistor ͑pMOSFET͒ performance has been reported with a standard Si complementary metal-oxide-semiconductor HfO 2 gate stack module. The Ge passivation is based on a thin, fully strained epitaxial Si layer grown on the Ge surface. We investigate in more detail how the device performance ͑hole mobility, I on , D it , V t , etc.͒ depends on the characteristics of this Si layer. We found that surface segregation of Ge through the Si layer takes place during the growth, which turns out to be determining for the interfacial trap density and distribution in the finalized gate stack. Based on a better understanding of the fundamentals of the Si deposition process, we optimize the process by switching to another Si precursor and lowering the deposition temperature. This results in a 4 times lower D it and improved device performance.Germanium has become a serious contender to replace silicon as the channel material in a sub-22 nm node complementary metaloxide-semiconductor ͑CMOS͒ for high performance technologies. A major bottleneck to this is the lack of a stable and easy-to-make germanium oxide ͑GeO 2 ͒ with good passivating properties for the interface between the channel and gate dielectric. This spurred a lot of research on passivation approaches ͑e.g., GeO 2 1-3 and GeON 4 ͒. One of the most successful passivation techniques for Ge MOS gate stacks appeared to be a thin, epitaxial layer of Si grown on top of the clean Ge surface, 5-9 also referred to as "SiH 4 annealing." 10 The idea behind this approach was to use the well-understood and highly developed passivation of Si/high-k dielectric interfaces, leading to highly performing Si MOS field-effect transistor devices, such as in Ref. 11. Although this approach was very successful, it turned out that this system was considerably more complex than a "simple" Si/high-k/metal gate system. The aim of this paper is to discuss some salient features of the Si passivation layer and how these features influence the characteristics of the MOS devices. We shall also discuss, which might even be more important in the end, how the growth process parameters influence these features and how the understanding of this process helps in optimizing the process, therefore improving the device performance. Si Passivation with a SiH 4 -Based Deposition ProcessWe present the growth process for the epitaxial Si layer on the Ge surface and the analysis results of this layer, followed by the electrical characterization of completed p-channel metal-oxidesemiconductor field-effect transistor ͑pMOSFET͒ devices.

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Section: Si Passivation With a Sih 4 -Based Deposition Processmentioning

confidence: 99%

The Influence of the Epitaxial Growth Process Parameters on Layer Characteristics and Device Performance in Si-Passivated Ge pMOSFETs

Caymax

Leys

Mitard

et al. 2009

J. Electrochem. Soc.

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“…Recent work at 500ºC has however shown that the growth rate of Si from SiH 4 , even in N 2 , is quasi zero, but the Si equivalent deposition rate in SiGe alloys with a Ge content of ~ 20 % (with the addition of GeH 4 ), also at 500ºC, reaches a value of 0.03 ML/sec in H 2 and shoots up to ~ 0.4 ML/sec in N 2 , see Fig. 1 right pane (15). This growth enhancement is caused by the faster H desorption from Ge sites, due to the weaker Ge-H bond (16).…”

Section: Epitaxial Growth Of the Si Capping Layer From Sihmentioning

confidence: 96%

The Influence of the Epitaxial Growth Process Parameters on Layer Characteristics and Device Performance in Si-passivated Ge pMOSFETs

Caymax

Leys²,

Mitard³

et al. 2009

ECS Trans.

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Recently, best 65 nm Ge pMOSFET performance has been reported (13) with a standard Si CMOS HfO 2 gate stack module. The Ge passivation is based on a thin, fully strained epitaxial Silayer grown on the Ge surface. We investigated in more detail how device performance (hole mobility, I on , V t etc) depends on the characteristics of this Si layer. We found that surface segregation of Ge through the Si layer takes place during the growth, which turns out to be determining for the interfacial trap density and distribution in the finalized gate stack. Based on a better understanding of the fundamentals of the Si deposition process, we optimized the process by switching to another Si precursor and lowering the deposition temperature. This resulted in a 4 times lower D it and in improved device performance.

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“…However, it is plagued by relatively slow Growth Rates (GR) at low temperatures, as confirmed by the following. Meanwhile, hydrogenated silicon precursors (such as silane (SiH4) [5], disilane (Si2H6) [6][7][8][9], trisilane (Si3H8) [10][11][12][13] or tetrasilane (Si4H10) [14][15]), yield significantly higher Si and SiGe growth rates at low temperatures. Such precursors are intrinsically non selective versus dielectric masking materials, but this difficulty can be overcome with advanced (Cyclic) Deposition / Etch processes [6], [16][17][18][19].…”

Section: -Introductionmentioning

confidence: 99%

A Benchmark of 300mm RP-CVD Chambers for the Low Temperature Epitaxy of Si and SiGe

et al. 2018

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We have assessed, in 300mm Reduced Pressure – Chemical Vapour Deposition chambers from major suppliers, the advantages and drawbacks of disilane for the low temperature growth of Si and SiGe. Si growth rates are, for T < 575°C, approximately ten times higher with Si2H6 than with SiH4, which are in turn roughly ten times higher than with SiH2Cl2. For given GeH4 and Si precursor mass-flow ratios, lower Ge contents and much higher SiGe growth rates are obtained at 550°C, 20 Torr with Si2H6 than with SiH4 and especially SiH2Cl2. Growth rates (Ge concentrations) are with SiH4 and SiH2Cl2 lower (slightly lower) in Supplier A than in Supplier B chamber. The situation is the opposite with Si2H6. This is assigned to (i) a ~ 5°C offset between the two and(ii) effective precursor flows which are different, most likely due to chamber geometry differences. Growth rate activation energies and relationships linking Ge concentration to precursor mass-flow ratios are quite similar, however, making process transfer between the two rather easy. Finally, we have compared ex-situ “HF-Last” wet cleanings and in-situ surface preparation processes for Si surface conditioning prior to epitaxy. Surfaces are after the latter always under high purity N2. This results in a threshold H2 bake temperature (above which there is no O interfacial contamination anymore) which is shifted downwards by ~ 25°C (from 775°C down to 750°C). Below that threshold, O sheet concentrations are with in-situ processes typically one third those associated with “HF-Last” wet cleanings and epitaxial surfaces are smoother.

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Si1−xGex growth using Si3H8 by low temperature chemical vapor deposition

Cited by 14 publications

References 15 publications

The Influence of the Epitaxial Growth Process Parameters on Layer Characteristics and Device Performance in Si-Passivated Ge pMOSFETs

The Influence of the Epitaxial Growth Process Parameters on Layer Characteristics and Device Performance in Si-Passivated Ge pMOSFETs

The Influence of the Epitaxial Growth Process Parameters on Layer Characteristics and Device Performance in Si-passivated Ge pMOSFETs

A Benchmark of 300mm RP-CVD Chambers for the Low Temperature Epitaxy of Si and SiGe

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