Shortest path CD measurement using contour extraction

Patterson, Oliver D.; Seefeldt, Bart; Liang, Wan-Hsiang; Hu, Haokun; Chen, Joan; Su, Yu-Chi; Yeh, Hsiang Ting; Zhang, Pengcheng

doi:10.1109/asmc.2018.8373165

Cited by 2 publications

(2 citation statements)

References 5 publications

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“…In the process of less than 10 nm, the new advanced CD-SEM technology is effectively applied to logic vias, complex overlay, HAR contacts, 3D morphology, etc. [ 415 , 416 , 417 ]…”

Section: Advanced Characterizations For Ultra-miniaturized Cmosmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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“…In the process of less than 10 nm, the new advanced CD-SEM technology is effectively applied to logic vias, complex overlay, HAR contacts, 3D morphology, etc. [ 415 , 416 , 417 ]…”

Section: Advanced Characterizations For Ultra-miniaturized Cmosmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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“…The advantages of CD-SEM makes the tool more useful in some form of continued applications. However, with the development of integrated circuits in the future, CD-SEM demands improving the resolution and assisting the modeling of OPC 2D graphics [227].…”

Section: Advanced Characterization For Ultra-miniaturized Cmosmentioning

confidence: 99%

Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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Shortest path CD measurement using contour extraction

Cited by 2 publications

References 5 publications

State of the Art and Future Perspectives in Advanced CMOS Technology

State of the Art and Future Perspectives in Advanced CMOS Technology

Miniaturization of CMOS

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