Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs

Meyer, J.; Kocan, Fatih

doi:10.1109/tvlsi.2007.893581

Cited by 18 publications

(21 citation statements)

References 19 publications

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“…Meyer and Kocan [1] proposed a novel logic block architecture, in which the configuration SRAMs of LUTs are shared among NPN-equivalent functions to reduce the number of configuration memory bits. Because the structures of these logic blocks are constructed on the basis of conventional LUTs, significant improvement was not achieved.…”

Section: Related Studiesmentioning

confidence: 99%

“…These systems are more flexible than application-specific integrated circuits (ASICs) and much faster than general-purpose processors in several application domains [1], [2]. Field programmable gate arrays (FPGAs), which are the most popular RLDs, are used for fine-grain operations and can be configured for implementing various digital circuits.…”

Section: Introductionmentioning

confidence: 99%

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COGRE: A Novel Compact Logic Cell Architecture for Area Minimization

Iida

Amagasaki

Okamoto

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYBecause of numerous circuit resources of FPGAs, there is a performance gap between FPGAs and ASICs. In this paper, we propose a small-memory logic cell, COGRE, to reduce the FPGA area. Our approach is to investigate the appearance ratio of the logic functions in a circuit implementation. Moreover, we group the logic functions on the basis of the NPN-equivalence class. The results of our investigation show that only small portions of the NPN-equivalence class can cover large portions of the logic functions used to implement circuits. Further, we found that NPN-equivalence classes with a high appearance ratio can be implemented by using a small number of AND gates, OR gates, and NOT gates. On the basis of this analysis, we develop COGRE architectures composed of several NAND gates and programmable inverters. The experimental results show that the logic area of 4-COGRE is smaller than that of 4-LUT and 5-LUT by approximately 35.79% and 54.70%, respectively. The logic area of 8-COGRE is 75.19% less than that of 8-LUT. Further, the total number of configuration memory bits of 4-COGRE is 8.26% less than the number of configuration memory bits of 4-LUT. The total number of configuration memory bits of 8-COGRE is 68.27% less than the number of configuration memory bits of 8-LUT.

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Section: Related Studiesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

COGRE: A Novel Compact Logic Cell Architecture for Area Minimization

Iida

Amagasaki

Okamoto

et al. 2012

IEICE Trans. Inf. & Syst.

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“…The use of NPN-equivalent classes removes the redundancy (because of LUTs) inherent to FPGAs with some compact high coverage logic blocks. Other researchers have attempted to optimize FPGA logic blocks on a coarser architecture level which include [14,15]. An SRAM [15] has been improved and further explored in this research work.…”

Section: Introductionmentioning

confidence: 99%

“…Other researchers have attempted to optimize FPGA logic blocks on a coarser architecture level which include [14,15]. An SRAM [15] has been improved and further explored in this research work. The main drawback of the logic blocks proposed in [9][10][11] is that they are derived on the basis of NPN-equivalent classes for a particular benchmark suite; hence, they offer high-end efficiency only for the circuits from which their NPN classes were derived.…”

Section: Introductionmentioning

confidence: 99%

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Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

Ali

Iqbal

Ahmed

et al. 2017

International Journal of Reconfigurable Computing

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In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases. In this paper, we first present a detailed analysis of a previously proposed FPGA architecture which allows sharing of LUTs memory (SRAM) tables among NPN-equivalent functions, to reduce the area as well as the number of configuration bits. We then propose several methods to improve the existing architecture. A new clustering technique has been proposed which packs NPN-equivalent functions together inside a Configurable Logic Block (CLB). We also make use of a recently proposed high performance Boolean matching algorithm to perform NPN classification. To enhance area savings further, we evaluate the feasibility of more than two LUTs sharing the same SRAM table. Consequently, this work explores the SRAM table sharing approach for a range of LUT sizes (4-7), while varying the cluster sizes (4-16). Experimental results on MCNC benchmark circuits set show an overall area reduction of ∼7% while maintaining the same critical path delay.

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A new FPGA architecture suitable for DSP applications

Wang¹,

Lai²,

Tong³

et al. 2011

J. Semicond.

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A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 m CMOS technology successfully. The die size is 6.3 4.5 mm 2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs.

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Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs

Cited by 18 publications

References 19 publications

COGRE: A Novel Compact Logic Cell Architecture for Area Minimization

COGRE: A Novel Compact Logic Cell Architecture for Area Minimization

Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

A new FPGA architecture suitable for DSP applications

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