SHARC: A streaming model for FPGA accelerators and its application to Saliency

Kestur, Srinidhi; Dantara, Dharav; Narayanan, Vijaykrishnan

doi:10.1109/date.2011.5763198

Cited by 12 publications

(9 citation statements)

References 15 publications

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“…The authors present a case-study by implementing the bio-inspired saliency-based visual attention system and demonstrate the benefits of run-time reconfiguration. Experimental results show about 5X speedup over an existing CPU implementation and up to 14X higher Performance-per-Watt over a relevant GPU implementation [3]. In that paper, each frame is processed as a new image and does not extract any features from consecutive images.…”

Section: Related Workmentioning

confidence: 92%

“…Because of this and the other advantages of the model, it is widely used in machine vision and robotics, and many hardware and software versions of it are implemented [3,6,7,8].…”

Section: Related Workmentioning

confidence: 99%

“…In [3] a streaming hardware accelerator with run-time configurability is presented. The authors present a case-study by implementing the bio-inspired saliency-based visual attention system and demonstrate the benefits of run-time reconfiguration.…”

Section: Related Workmentioning

confidence: 99%

“…Software realization of this model runs serially, although it is biologically inspired. Recent research shows that implementation of an algorithm on a hardware platform results in better scalability, speed, power consumption, and accuracy, because of its parallelism [3].…”

Section: Introductionmentioning

confidence: 99%

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Fast saliency map extraction from video: A hardware approach

Moradhasel

Araabi

Fakhraie

et al. 2013

2013 8th Iranian Conference on Machine Vision and Image Processing (MVIP)

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Saliency map is a central part of many visual attention systems, particularly during learning and control of bottom-up attention. In this research we developed a hardware tool to extract saliency map from a video sequence. Saliency map is obtained by aggregating primary features of each frame, such as intensity, color, and lines orientation, along with temporal difference. The system is designed to provide both high speed and acceptable accuracy for real-time applications, such as machine vision and robotics. A versatile Verilog model for realization of the video processing system is developed, which can easily be mapped and synthesized on various FPGA or ASIC platforms. The proposed parallel hardware can process over 50 million pixels in a second, which is about 2x faster than the state-of-theart designs. Experimental results on sample images justify the applicability and efficiency of the developed system in real-time applications.

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Section: Related Workmentioning

confidence: 92%

“…Because of this and the other advantages of the model, it is widely used in machine vision and robotics, and many hardware and software versions of it are implemented [3,6,7,8].…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Fast saliency map extraction from video: A hardware approach

Moradhasel

Araabi

Fakhraie

et al. 2013

2013 8th Iranian Conference on Machine Vision and Image Processing (MVIP)

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“…Dedicated applicationspecific integrated circuits (ASIC) and field-programmable-gatearrays (FPGA) are often used, in addition to personal computers (PC) and digital signal processors (DSP). FPGAs [9] and ASICs [10,11] became popular tools for image processing, thanks to superior performance and shorter execution time compared to standard PCs and DSPs. The FPGA design offers more flexibility, which is demonstrated in designs of dedicated filtering blocks [8,12] or multiprocessor implementations [13].…”

Section: Introduction and Related Workmentioning

confidence: 99%

A low-power 490 mpixels/s hardware accelerator for pyramidal decomposition of images

Popović

Leblebici

2015

2015 IEEE International Conference on Image Processing (ICIP)

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This paper introduces a pyramidal decomposition system suitable for high frame rate and real-time applications. The presented system's architecture omits the image transpose block used in standard separable filters, and implements internal downsampling to reduce number of computations. The decomposition is implemented in form of a field programmable gate array (FPGA) hardware accelerator and the presented results show the low resource utilization of the design. The internal downsampling reduces the power consumption by an order of magnitude compared to state-of-the-art, which makes this accelerator an excellent addition to co-processors on mobile platforms.

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